Simultaneous Peak and Average Power Minimization during Datapath Scheduling for DSP Processors

The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using deep submicron and nanometer technology, the peak power, peak power differential, average power and total energy are equally critical design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power while maintaining performance by use of dynamic frequency clocking and multiple supply voltages. The algorithms use integer linear programming based models. The dynamic frequency clocking methodology is more useful for data intensive signal processing applications. The effectiveness of our scheduling technique is measured by estimating the peak power consumption, the average power consumption and the power delay product of the datapath circuit. Furthermore, the proposed scheduling scheme is compared with combined multiple supply voltages and multicycling scheme. Experimental results show that combined multiple supply voltages ( 0 ) and dynamic frequency clocking scheme achieves significant reductions in peak power ( on the average), average power ( on the average) and power delay product ( on the average). Categories and Subject Descriptors B.5.1 [Register-Transfer-Level Implementation]: Datapath Design; B.5.2 [Register-Transfer-Level Implementation]: Automatic Synthesis, Optimization; G.1.6 [Numerical Analysis]: Optimization, Integer Programming General Terms Algorithms, Performance, Design, Reliability Keywords Peak power, Average Power, High-level Synthesis, Datapath Scheduling, Multiple Voltages, Dynamic Frequency Clocking Permission to make digital or hard copies of all or part of this work for ..

An ILP-Based Scheduling Scheme for Energy Efficient High Performance Datapath Synthesis

In this paper, we describe an integer linear programming (ILP) based datapath scheduling algorithm which uses both multiple supply voltages and dynamic frequency clocking for power optimization. The scheduling technique assumes the number and type of different functional units as resource constraints and minimizes the energy delay product (EDP). The energy savings directly comes from the use of multiple supply voltages and the performance improvement from dynamic frequency clocking. The algorithm has been applied to various high level synthesis benchmark circuits under different resource constraints. The experimental results show that under various resource constraints using two supply voltage levels , the average energy reduction is the average EDP reduction is

ILP Models for Simultaneous Energy and Transient Power Minimization during Behavioral Synthesis

this paper, we propose an ILP-based framework for the reduction of energy and transient power through datapath scheduling during behavioral synthesis. A new metric called "modified cycle power function" (CPF ) is defined that captures the above power characteristics and facilitates integer linear programming formulations. The ILP-based datapath scheduling schemes with CPF as objective function are developed assuming three modes of datapath operation, such as, single supply voltage and single frequency (SVSF), multiple supply voltages and dynamic frequency clocking (MVDFC), and multiple supply voltages and multicycling (MVMC). We conducted experiments on selected high-level synthesis benchmark circuits for various resource constraints and estimated power, energy and energy delay product for each of them. Experimental results show that significant reductions in power, energy and energy delay product can be obtained. Categories and Subject Descriptors: B.5.1 [Register-Transfer-Level Implementation]: Datapath Design; B.5.2 [Register-Transfer-Level Implementation]: Automatic Synthesis, Optimization; G.1.6 [Numerical Analysis]: Optimization, Integer Programming General Terms: Algorithms, Performance, Design, Reliability, Linear Modeling of Non-linearity, Scheduling Additional Key Words and Phrases: peak power, cycle difference power, peak power differential, average power, multiple supply voltages, dynamic frequency clocking, multicycling, datapath scheduling 1