On the effect of nano-injectors on conduction in silicon p-i-n diodes

P–i–n diodes are widely used in power electronics [1-2], solar cells [3], light detection [4] and also light generation [5]. Contrary to the case of light detection or conversion, light generation is usually achieved by biasing the device in forward mode, in a condition of carrier injection. Depending on its level, the device can operate in regimes controlled by respectively generation/recombination current, diffusion current or the so called series resistance [6]. The injection level also controls the balance between the recombination mechanisms, and it is commonly controlled via the applied bias, which could be fixed by the specific application rather then being a free parameter. A possible approach to better control the injection level is to modify the features of the carrier injectors, for instance by thinning down the junction area [7] or reducing the injectors itself to a nanometer scale [8]. A practical way to realize nano-injectors is to embed the intrinsic region in oxide and create the connection between the intrinsic region and the two extension regions via antifuses, as realized in [9]. The size and properties of the antifuses can be controlled electrically, making it suitable to analyze the effects of progressive scaling of the dimensions of carrier injectors. In this work, we compare electrical behaviors of a standard p-i-n diode with antifuse p-i-n diodes programmed at different conditions. Electrical I-V measurements are performed at temperatures between -20 and 200 °C (I-V-T characteristics) in order to investigate the dominant mechanisms in the conduction

Reducing AC impedance measurement errors caused by the DC voltage dependence of broadband high-voltage bias-tees

During the AC impedance characterization of devices, from the kHz-range up to the GHz-range, accuracy can be lost when a DC voltage is applied. Commercial high-voltage broadband bias-tees are often voltage-dependent, which can cause inaccuracies at low frequencies. A calibration technique with applied bias significantly improves the measurement accuracy.\ud Additionally, a bias-tee has been developed with a voltageindependent capacitor, suitable for DC voltages up to 500 V showing excellent performance up to several gigahertz. PIN diode limiters protect the measurement equipment from damage in case of a device breakdown.\u

Strong efficiency improvement of SOI-LEDs through carrier confinement

Contemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts. In this letter, we present a new device structure where the carrier injection takes place through silicon slabs of only a few nanometer thick. Its external quantum efficiency of 1.4 • 10−4 at room temperature, with a spectrum peaking at 1130 nm, is almost two orders higher than reported thus far on SOI. The structure diminishes the dominant role of nonradiative recombination at the n+ and p+contacts, by confining the injected carriers in an SOI peninsula.\ud With this approach, a compact infrared light source can be fabricated using standard semiconductor processing steps.\u

Gate-capacitance extraction from RF C-V measurements

In this work, a full two-port analysis of an RF C-V measurement set-up is given. This two-port analysis gives insight on the limitations of the commonly used gate capacitance extraction, based on the Y/sub 11/ parameter of the device. It is shown that the parasitics of the device can disturb the extracted gate capacitance and a new extraction scheme, based on the Z-matrix, is introduced that eliminates the effect of these parasitics. Measurement results prove the validity of this new extraction scheme, under different conditions

The Cotton and Sugar Subsidies Decisions: WTO's Dispute Settlement System Rebalances the Agreement on Agriculture

Agricultural and Food Policy, International Relations/Trade,

Fast RF-CV characterization through high-speed 1-port S-parameter measurements

We present a novel method to measure the capacitance-voltage relation of an electronic device. The approach is accurate, very fast, and cost-effective compared to the existing off-the-shelf solutions. Capacitances are determined using a single-frequency 1-port S-parameter setup constructed from discrete components. We introduce a new way to correct for non-linearities of the used components, which greatly increases the accuracy with which the phase and magnitude of the reflected signal is measured. The measurement technique is validated on an RF-MEMS capacitive switch and a BST tunable capacitor. Complete capacitance-voltage curves are measured in less than a millisecond, with a measurement accuracy well below 1%.\ud \u

An Initial study on The Reliability of Power Semiconductor Devices

An initial literature study combined with some basic comparative simulations has been performed on different electricfield modulation techniques and the subsequent reliability issues are reported for power semiconductor devices. An explanation of the most important power device metrics such as the offstate breakdown (BV) and specific on-resistance (RON) will be given, followed by a short overview of some of the electrostatic techniques (fieldplates, RESURF e.g. [1]) used to suppress peak electric fields. Furthermore it will be addressed that the high current operation of these devices results in shifting electric field peaks (Kirk effect [2], [3]) and as such different avalanche behavior, resulting in (gate oxide) reliability issues unlike those of conventional CMOS

Four point probe structures with buried electrodes for the electrical characterization of ultrathin conducting films

Test structures for the electrical characterization of ultrathin conductive (ALD) films are presented based on buried electrodes on which the ultrathin film is deposited.\ud This work includes test structure design and fabrication, and the electrical characterization of ALD TiN films down to 4 nm. It is shown that these structures can be used successfully to characterize sub 10 nm films.\u

Type-I Seesaw as the Common Origin of Neutrino Mass, Baryon Asymmetry, and the Electroweak Scale

The type-I seesaw represents one of the most popular extensions of the Standard Model. Previous studies of this model have mostly focused on its ability to explain neutrino oscillations as well as on the generation of the baryon asymmetry via leptogenesis. Recently, it has been pointed out that the type-I seesaw can also account for the origin of the electroweak scale due to heavy-neutrino threshold corrections to the Higgs potential. In this paper, we show for the first time that all of these features of the type-I seesaw are compatible with each other. Integrating out a set of heavy Majorana neutrinos results in small masses for the Standard Model neutrinos; baryogenesis is accomplished by resonant leptogenesis; and the Higgs mass is entirely induced by heavy-neutrino one-loop diagrams, provided that the tree-level Higgs potential satisfies scale-invariant boundary conditions in the ultraviolet. The viable parameter space is characterized by a heavy-neutrino mass scale roughly in the range $10^{6.5\cdots7.0}$ GeV and a mass splitting among the nearly degenerate heavy-neutrino states up to a few TeV. Our findings have interesting implications for high-energy flavor models and low-energy neutrino observables. We conclude that the type-I seesaw sector might be the root cause behind the masses and cosmological abundances of all known particles. This statement might even extend to dark matter in the presence of a keV-scale sterile neutrino.Comment: 41 pages, 5 figures, matches version published in PR