A Model Checking based Converter Synthesis Approach for Embedded Systems

Protocol conversion problem involves identifying whether two or more protocols can be composed with or without an intermediary, referred to as a converter, to obtain a pre-specified desired behavior. We investigate this problem in formal setting and propose, for the first time, a temporal logic based automatic solution to the convertibility verification and synthesis. At its core, our technique is based on local model checking technique and determines the existence of the converter and if a converter exists, it is automatically synthesized. A number of key features of our technique distinguishes it from all existing formal and/or informal techniques. Firstly, we handle both data and control mismatches (for the first time), using a single unifying model checking based solution. Secondly, the proposed approach uses temporal logic for the specification of correct behaviors (unlike earlier automaton based specifications) which is both elegant and natural to express event ordering and data-matching requirements. Finally, we have have experimented extensively with the examples available in the existing literature to evaluate the applicability of our technique in wide range of applications

Timing analysis of synchronous programs using WCRT Algebra: Scalability through abstraction

Synchronous languages are ideal for designing safety-critical systems. Static Worst-Case Reaction Time (WCRT) analysis is an essential component in the design flow that ensures the real-time requirements are met. There are a few approaches for WCRT analysis, and the most versatile of all is explicit path enumeration. However, as synchronous programs are highly concurrent, techniques based on this approach, such as model checking, suffer from state explosion as the number of threads increases. One observation on this problem is that these existing techniques analyse the program by enumerating a functionally equivalent automaton while WCRT is a non-functional property. This mismatch potentially causes algorithm-induced state explosion. In this paper, we propose a WCRT analysis technique based on the notion of timing equivalence, expressed using WCRT algebra. WCRT algebra can effectively capture the timing behaviour of a synchronous program by converting its intermediate representation Timed Concurrent Control Flow Graph (TCCFG) into a Tick Cost Automaton (TCA), a minimal automaton that is timing equivalent to the original program. Then the WCRT is computed over the TCA. We have implemented our approach and benchmarked it against state-of-the-art WCRT analysis techniques. The results show that the WCRT algebra is 3.5 times faster on average than the fastest published technique.</jats:p

Tight WCRT Analysis for Synchronous C Programs

Accurate estimation of the tick length of a synchronous program is essential for efficient and predictable implementations that are devoid of timing faults. The techniques to determine the tick length statically are classified as worst case reaction time (WCRT) analysis. While a plethora of techniques exist for worst case execution time (WCET) analysis of procedural programs, there are only a handful of techniques for determining the WCRT value of synchronous programs. Most of these techniques produce overestimates and hence are unsuitable for the design of systems that are predictable while being also efficient. In this paper, we present an approach for the accurate estimation of the exact WCRT value of a synchronous program, called its tight WCRT value, using model checking. For our input specifications we have selected a synchronous C based language called PRET-C that is designed for programming Precision Timed (PRET) architectures. We then present an approach for static WCRT analysis of these programs via an intermediate format called TCCFG. This intermediate representation is then compiled to produce the input for the model checker. Experimental results that compare our approach to existing approaches demonstrate the benefits of the proposed approach. The proposed approach, while presented for PRET-C is also applicable for WCRT analysis of Esterel using simple adjustments to the generated model. The proposed approach thus paves the way for a generic approach for determining the tight WCRT value of synchronous programs at compile time

Designing Neural Networks for Real-Time Systems

Artificial Neural Networks (ANNs) are increasingly being used within safety-critical Cyber-Physical Systems (CPSs). They are often co-located with traditional embedded software, and may perform advisory or control-based roles. It is important to validate both the timing and functional correctness of these systems. However, most approaches in the literature consider guaranteeing only the functionality of ANN based controllers. This issue stems largely from the implementation strategies used within common neural network frameworks -- their underlying source code is often simply unsuitable for formal techniques such as static timing analysis. As a result, developers of safety-critical CPS must rely on informal techniques such as measurement based approaches to prove correctness, techniques that provide weak guarantees at best. In this work we address this challenge. We propose a design pipeline whereby neural networks trained using the popular deep learning framework Keras are compiled to functionally equivalent C code. This C code is restricted to simple constructs that may be analysed by existing static timing analysis tools. As a result, if compiled to a suitable time-predictable platform all execution bounds may be statically derived. To demonstrate the benefits of our approach we execute an ANN trained to drive an autonomous vehicle around a race track. We compile the ANN to the Patmos time-predictable controller, and show that we can derive worst case execution timings.Comment: 4 pages, 2 figures. IEEE Embedded Systems Letters, 202

Precise specification matching for adaptive reuse in embedded systems

AbstractSpecification matching is a key to reuse of components in embedded systems. Existing specification matching techniques for embedded systems are designed to match reactive behaviors using adaptive techniques to dynamically alter behaviors. However, correct specification matching demands both behavioral matching (that checks component adaptability) and functional matching (that ensures that proper functionality is reused). While approaches for behavioral matching exist, combined functional and behavioral matching during component reuse in embedded systems is lacking. This paper presents a precise specification matching, including both behavioral and functional matching. We introduce attributed labeled transition systems (ALTS) to formally specify component behavior and functionalities. Given ALTS of a new specification (a function F) and an existing component (a device D), a new refinement relation from F to D, called an S-matching relation, is proposed for precise specification matching. The existence of an S-matching relation is also shown to be a necessary and sufficient condition for the existence of a correct adapter to adapt D to match F both behaviorally and functionally. Automated component adaptation is facilitated by a matching tool implemented in a tabled logic programming environment, which provides distinct advantages for rapid implementation. Practical examples are given to illustrate how the concrete adapter is derived automatically from specification matching

1 A Model Checking based Converter Synthesis Approach for Embedded Systems

Protocol conversion problem involves identifying whether two or more protocols can be composed with or without an intermediary, referred to as a converter, to obtain a pre-specified desired behavior. We investigate this problem in formal setting and propose, for the first time, a temporal logic based automatic solution to the convertibility verification and synthesis. At its core, our technique is based on local model checking technique and determines the existence of the converter and if a converter exists, it is automatically synthesized. A number of key features of our technique distinguishes it from all existing formal and/or informal techniques. Firstly, we handle both data and control mismatches (for the first time), using a single unifying model checking based solution. Secondly, the proposed approach uses temporal logic for the specification of correct behaviors (unlike earlier automaton based specifications) which is both elegant and natural to express event ordering and data-matching requirements. Finally, we have have experimented extensively with the examples available in the existing literature to evaluate the applicability of our technique in wide range of applications.

Functional Decomposition of Composite Finite State Machines

. Many of the multiway general decompositions of finite state machines (FSMs) proposed in the past are concerned with the cost reduction of the eventual logic level implementation. In this paper we propose a new method of decomposing a new FSM model called Composite Finite State Machines (CFSMs), which is ideal for use in a microprocessor based system design environment. Our algorithm partitions the CFSM of the design functionality into a set of interacting CFSMs such that the partitioned CFSMs represent the different sub-functions of the design specification. Unlike existing FSM decomposition schemes, our algorithm is bottom-up and is able to determine suitable devices from a design library to implement the partitioned sub-functions. It is an extension of the behavioural mapping procedure proposed in [12] which addressed the implementability question for a single design function by mapping to a particular device, whereas our algorithm performs a behavioural mapping between a design fu..

Hidden Time Model for Specification and Verification of Embedded Systems

Embedded systems are application specific digital systems that are usually designed using a microprocessor along with a set of programmable hardware and software components. Since these systems are real-time in nature, specification of temporal constraints is a key issue. We have recently proposed the CFSMcharts language for component-based specification of these systems. However, this proposal had no features to specify quantitative temporal constraints that are crucial to embedded systems specification. In this paper, we propose a new model of time, called hidden time, for specification of temporal constraints in CFSMcharts and contrast it to existing schemes. The proposed scheme is hierarchical and hides away the quantitative temporal constraints from the top level specification. This leads to a simpler style for the specification of these constraints and simpler semantics for the top level specification. Another major contribution of the proposed scheme is that, properties to be v..