Temperature Dependent Border Trap Response Produced by a Defective Interfacial Oxide Layer in Al₂O₃/InGaAs Gate Stacks

Intentional oxidation of an As₂-decapped (100) In_0.57Ga_0.43As substrate by additional H₂O dosing during initial Al₂O₃ gate dielectric atomic layer deposition (ALD) increases the interface trap density (<i>D</i>_it), lowers the band edge photoluminescence (PL) intensity, and generates Ga-oxide detected by X-ray photoelectron spectroscopy (XPS). Aberration-corrected high resolution transmission electron microscopy (TEM) reveals formation of an amorphous interfacial layer which is distinct from the Al₂O₃ dielectric and which is not present without the additional H₂O dosing. Observation of a temperature dependent border trap response, associated with the frequency dispersion of the accumulation capacitance and conductance of metal-oxide-semiconductor (MOS) structures, is found to be correlated with the presence of this defective interfacial layer. MOS capacitors prepared with additional H₂O dosing show a notable decrease (∼20%) of accumulation dispersion over 5 kHz to 500 kHz when the measurement temperature decreases from room temperature to 77 K, while capacitors prepared with an abrupt Al₂O₃/InGaAs interface display little change (<2%) with temperature. Similar temperature-dependent border trap response is also observed when the (100) InGaAs surface is treated with a previously reported HCl­(aq) wet cleaning procedure prior to Al₂O₃ ALD. These results point out the sensitivity of the temperature dependence of the border trap response in metal oxide/III–V MOS gate stacks to the presence of processing-induced interface oxide layers, which alter the dynamics of carrier trapping at defects that are not located at the semiconductor interface

Dual Passivation of Intrinsic Defects at the Compound Semiconductor/Oxide Interface Using an Oxidant and a Reductant

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures

Interface Defect Hydrogen Depassivation and Capacitance–Voltage Hysteresis of Al₂O₃/InGaAs Gate Stacks

We investigate the effects of pre- and postatomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al₂O₃/InGaAs gate stacks. Reliability is characterized by capacitance–voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial capability to passivate both interface and border traps, a final forming gas (H₂/N₂) anneal (FGA) step is correlated with a significant hysteresis. This appears to be caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. On the other hand, intentional air exposure of the InGaAs surface prior to Al₂O₃ ALD increases the initial interface trap density (<i>D</i>_it) but considerably lowers the hysteresis

Passivation of InGaAs(001)-(2 × 4) by Self-Limiting Chemical Vapor Deposition of a Silicon Hydride Control Layer

A saturated Si–H_<i>x</i> seed layer for gate oxide or contact conductor ALD has been deposited via two separate self-limiting and saturating CVD processes on InGaAs(001)-(2 × 4) at substrate temperatures of 250 and 350 °C. For the first self-limiting process, a single silicon precursor, Si₃H₈, was dosed at a substrate temperature of 250 °C, and XPS results show the deposited silicon hydride layer saturated at about 4 monolayers of silicon coverage with hydrogen termination. STS results show the surface Fermi level remains unpinned following the deposition of the saturated silicon hydride layer, indicating the InGaAs surface dangling bonds are electrically passivated by Si–H_<i>x</i>. For the second self-limiting process, Si₂Cl₆ was dosed at a substrate temperature of 350 °C, and XPS results show the deposited silicon chloride layer saturated at about 2.5 monolayers of silicon coverage with chlorine termination. Atomic hydrogen produced by a thermal gas cracker was subsequently dosed at 350 °C to remove the Si–Cl termination by replacing with Si–H termination as confirmed by XPS, and STS results confirm the saturated Si–H_<i>x</i> bilayer leaves the InGaAs(001)-(2 × 4) surface Fermi level unpinned. Density function theory modeling of silicon hydride surface passivation shows an Si–H_<i>x</i> monolayer can remove all the dangling bonds and leave a charge balanced surface on InGaAs

Growth Optimization, Optical, and Dielectric Properties of Heteroepitaxially Grown Ultrawide-Bandgap ZnGa2O4 (111) Thin Film

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