Many Topological Insulators Fail the Surface Conduction Test

In this report, we scrutinize the thickness dependent resistivity data from the recent literature on electrical transport measurements in topological insulators. A linear increase in resistivity with increase in thickness is expected in the case of these materials since they have an insulating bulk and conducting surface. However, such a trend is not seen in the resistivity versus thickness data for all the cases examined, except for some samples, where it holds for a narrow range of thickness.Comment: 11 pages, 3 figure

Execution history guided instruction prefetching

The increasing gap in performance between processors and main memory has made effective instructions prefetching techniques more important than ever. A major deficiency of existing prefetching methods is that most of them require an extra port to I-cache. A recent study by [19] shows that this factor alone explains why most modern microprocessors do not use such I-cache hardware-based I-cache prefetch schemes. The contribution of this paper is two-fold. First we present a method that does not require an extra port to I-cache

Global partitioning of parallel loops and data arrays for caches and distributed memory in multiprocessors

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 49-50).by Rajeev K. Barua.M.S

Compiler-managed memory system for software-exposed architectures

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 155-161).Microprocessors must exploit both instruction-level parallelism (ILP) and memory parallelism for high performance. Sophisticated techniques for ILP have boosted the ability of modern-day microprocessors to exploit ILP when available. Unfortunately, improvements in memory parallelism in microprocessors have lagged behind. This thesis explains why memory parallelism is hard to exploit in microprocessors and advocate bank-exposed architectures as an effective way to exploit more memory parallelism. Bank exposed architectures are a kind of software-exposed architecture: one in which the low level details of the hardware are visible to the software. In a bank-exposed architecture, the memory banks are visible to the software, enabling the compiler to exploit a high degree of memory parallelism in addition to ILP. Bank-exposed architectures can be employed by general-purpose processors, and by embedded chips, such as those used for digital-signal processing. This thesis presents Maps, an enabling compiler technology for bank-exposed architectures. Maps solves the problem of bank-disambiguation, i.e., how to distribute data in sequential programs among several banks to best exploit memory parallelism, while retaining the ability to disambiguate each data reference to a particular bank. Two methods for bank disambiguation are presented: equivalence-class unification and modulo unrolling. Taking a sequential program as input, a bank-disambiguation method produces two outputs: first, a distribution of each program object among the memory banks; and second, a bank number for every reference that can be proven to access a single, known bank for that data distribution. Finally, the thesis shows why non-disambiguated accesses are sometimes desirable. Dependences between disambiguated and non-disambiguated accesses are enforced through explicit synchronization and software serial ordering. The MIT Raw machine is an example of a software-exposed architecture. Raw exposes its ILP, memory and communication mechanisms. The Maps system has been implemented in the Raw compiler. Results on Raw using sequential codes demonstrate that using bank disambiguation in addition to ILP improves performance by a factor of 3 to 5 over using ILP alone.by Rajeev Barua.Ph.D

Easy PRAM-based High-performance Parallel Programming with ICE

A poster of this paper will be presented at the 25th International Conference on Parallel Architecture and Compilation Technology (PACT ’16), September 11-15, 2016, Haifa, Israel.Parallel machines have become more widely used. Unfortunately parallel programming technologies have advanced at a much slower pace except for regular programs. For irregular programs, this advancement is inhibited by high synchronization costs, non-loop parallelism, non-array data structures, recursively expressed parallelism and parallelism that is too fine-grained to be exploitable. We present ICE, a new parallel programming language that is easy-to-program, since: (i) ICE is a synchronous, lock-step language; (ii) for a PRAM algorithm its ICE program amounts to directly transcribing it; and (iii) the PRAM algorithmic theory offers unique wealth of parallel algorithms and techniques. We propose ICE to be a part of an ecosystem consisting of the XMT architecture, the PRAM algorithmic model, and ICE itself, that together deliver on the twin goal of easy programming and efficient parallelization of irregular programs. The XMT architecture, developed at UMD, can exploit fine-grained parallelism in irregular programs. We built the ICE compiler which translates the ICE language into the multithreaded XMTC language; the significance of this is that multi-threading is a feature shared by practically all current scalable parallel programming languages. As one indication of ease of programming, we observed a reduction in code size in 7 out of 11 benchmarks vs. XMTC. For these programs, the average reduction in number of lines of code was when compared to hand optimized XMTC The remaining 4 benchmarks had the same code size. Our main result is perhaps surprising: The run-time was comparable to XMTC with a 0.76% average gain for ICE across all benchmarks.NSF award 116185

Evaluation of the efficacy of tamsulosin with or without deflazacort for stone clearance after extracorporeal shockwave lithotripsy for upper ureteral and renal calculi

Background: Medical expulsive therapy in the form of alpha blockers, corticosteroids, calcium channel blockers is being used with success for medical treatment of lower ureteric calculus. Adjunctive use of these therapeutic agents in post extracorporeal shockwave lithotripsy period is also being tried.With this background, we evaluated the efficacy of tamsulosin with or without deflazacort for various outcome factors after ESWL of upper ureteral and renal calculi.Methods: A Prospecive study during period from February 2014 to April 2015 including a total of 90 patients with solitary upper ureteral or renal calculus who underwent ESWL was conducted. Patients were divided into three groups. Group A(30 patients) were given standard therapy (analgesics and antibiotics for 5 days), Group B (30 patients) were given standard plus tamsulosin (0.4 mg once daily) for 4 weeks and Group C (30 patients) were given standard therapy plus tamsulosin (0.4 mg once daily) and deflazacort (6 mg twice daily) for 4 weeks . Patients were evaluated at 2 and 4 weeks post ESWL with X ray KUB and USG.Results: At the end of 4 weeks, 10, 17, and 26 patients in group A, B and C respectively cleared their stones. Out of these 2, 6 and 19 patients in group A, B and C respectively cleared their stones in first 2 weeks. Clearance in group C was significantly higher as compared to group A and B.Conclusions: Addition of alpha-blocker tamsulosin along with deflazacort post ESWL for renal and upper ureteric calculi increases the stone expulsion rate and reduces the expulsion duration as shown by highly statistically significant results in group C.

Retrofitting Security in COTS Software with Binary Rewriting

We present a practical tool for inserting security features against low-level software attacks into third-party, proprietary or otherwise binary-only software. We are motivated by the inability of software users to select and use low-overhead protection schemes when source code is unavailable to them, by the lack of information as to what (if any) security mechanisms software producers have used in their toolchains, and the high overhead and inaccuracy of solutions that treat software as a black box. Our approach is based on SecondWrite, an advanced binary rewriter that operates without need for debugging information or other assist. Using SecondWrite, we insert a variety of defenses into program binaries. Although the defenses are generally well known, they have not generally been used together because they are implemented by different (non-integrated) tools. We are also the first to demonstrate the use of such mechanisms in the absence of source code availability. We experimentally evaluate the effectiveness and performance impact of our approach. We show that it stops all variants of low-level software attacks at a very low performance overhead, without impacting original program functionality

The compiler for the XMTC parallel language: Lessons for compiler developers and in-depth description

In this technical report, we present information on the XMTC compiler and language. We start by presenting the XMTC Memory Model and the issues we encountered when using GCC, the popular GNU compiler for C and other sequential languages, as the basis for a compiler for XMTC, a parallel language. These topics, along with some information on XMT specific optimizations were presented in [10]. Then, we proceed to give some more details on how outer spawn statements (i.e., parallel loops) are compiled to take advantage of XMT’s unique hardware primitives for scheduling flat parallelism and how we incremented this basic compiler to support nested parallelism

Role of serum CA 19-9 as a tumor marker in TCC bladder

Background: There is a dearth of reliable blood and urine markers for transitional cell carcinoma of urinary bladder. CA 19-9 is a well-known marker for gastrointestinal malignancies and is being investigated for other malignancies including carcinoma bladder. In this prospective study, we evaluated the role of serum CA 19-9 as a tumor marker and correlated its level with tumor grade and stage.Methods: One hundred and fifteen patients with transitional cell carcinoma of urinary bladder and 69 healthy volunteers, as controls were included in the study. Preoperative blood sample was analysed for level of CA 19-9 using ELISA kit (normal - 0 U/ml to 37U/ml) and were correlated with grade and TNM stage of tumor.Results: The range of the control group is 2-38U/ml (mean: 17.67±9.68U/ml); TCC group is 1-94U/ml (mean: 37.12±31.52U/ml) (p=0.304). When CA 19-9 level >37IU/ml was taken as cut-off for a positive test, sensitivity of detecting T3 disease, T4 disease, MIBC, presence of node and high grade tumour were 80%, 75%, 70.3%, 78% and 57.8% respectively. However, there was a statistically significant increase in levels of CA19-9 in relation to higher grade (<0.001), presence of muscle invasion (<0.001), T stage (<0.001) and N stage (<0.001).Conclusions: Serum CA19-9 is almost invariably raised in patients with high grade and invasive disease. Thus, it has a place as a prognostic marker rather than as a diagnostic tool due to its low sensitivity for TCC bladder