IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS

The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %

Design Of A 16- Bit adder Decoder Application Circuit

The aim of this paper is the design of an adder which relates to error checking and updating circuits required for the analysis of decoder circuits. The parameters such as Delay, Power dissipation, and PDP are usually considered in the design process. The proposed adder circuit uses dynamic logic technique and designed with pass transistor logic TTL configuration. The reduction of components is achieved as two transistors for every logic cell using the dynamic logic design. The proposed adder is implemented in 16 bit by cascading the adder circuit using the carry select adder technique and considering the parameters of delay, power dissipation, and throughput. The generated layout was simulated using VLSI CAD tools for 70 nm and 180 nm feature sizes. The proposed circuit results reflected the intention of having a lower power dissipation of 7.5 nW, reduced delay of 0.127 ns and a throughput of 3.69×109 Gbps. This study emphasised that the proposed design resulted in a better output

Low power and low voltage SRAM design for LDPC codes hardware applications

The Low Voltage Low Power (LVLP) 8T, 11T, 13T and ZA SRAM cell is designed using the dynamic logic SRAM cell. The SRAM cells are implemented using pass transistor logic technique, which is mainly focused on read and write operation. The circuits are designed by using DSCH2 circuit editor and their layouts are generated by MICROWIND3 layout editor. The Layout Versus Simulation (LVS) design has been verified using BSIM 4 with 65nm technology and with a corresponding voltage of 0.7V respectively. The simulated SRAM layouts are verified and analyzed. The SRAM 8T gives power dissipation of 0.145 microwatts, propagation delay of 37.2 pico seconds, area of 14 × 8 micrometers and a throughput of 4.037 nano seconds

Improved speed low power and low voltage SRAM design for LDPC application circuits

The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %

Low Power and 5.8 GHz Operating Frequency of Digital Frequency Divider Using Proposed Sequential Circuit

Background: The frequency divider is a critical element in ultra-high-speed applications of communication systems, which provides an important benchmark for the performance of high-speed technology. These frequency divider designs are based on CMOS technology and contain many newer gate configurations and device functions, which achieved in terms of high speed, low power dissipation and reduced chip size, which is a negative element that should be lowered at all costs to maintain high speed technological requirements. Objective: To design a 1/3 and 1/5 frequency divider circuit by using proposed JK flip-flop. To anaylse the power dissipation, maximum operating frequency and propagation delay. Results: Compared with conventional techniques, the proposed JK Flip-Flop based frequency divider circuit has a maximum operating frequency of 59.38GHz with 0.192 mW of power utilisation. Conclusion: the proposed design outperformed a comparable CMOS circuit in term of power dissipation, propagation delay, layout area and operating frequency. The circuit is designed using digital schematic CAD tools, while a layout editor is used for the layout generation. Layout versus simulation (LVS) is performed by a BSIM 4 analyser. This paper also presents the result of parametric analysis, including measured power dissipation and leakage current through the load capacitance and supply voltages that gives better performance than existing circuits