An 8-bit 100-Mhz full-Nyquist analog-to-digital converter

\u3cp\u3eAn 8-bit 100-MHz full-Nyquist analog-to-digital (A/D) converter using a folding and interpolation architecture is presented. In a folding system a multiple use of comparator stages is implemented. A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. However, every quantization level requires a folding stage, thus no reduction in input circuitry is found. Interpolation between the outputs of the folding stages generates additional folding signals without the need for input stages. A reduction in input circuitry equal to the number of interpolations is obtained. The folding and interpolation architecture leads to a compact, high-performance A/D converter system. In an oxide isolated bipolar process the 8-bit converter is implemented, requiring 800 mW from a single 5.2-V supply. Die size is 3.2 X 3.8 mm2. Up until now no real theoretical description of the speed limitation of flash-type A/D converters has existed. A high-level model describing distortion caused by timing errors is presented. Considering clock timing accuracies needed to obtain the speed requirement, this distortion is thought to be the main speed limitation. This model has been used to optimize the effective resolution bandwidth of the converter.\u3c/p\u3

An 80 MHz, 80 mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technolog

A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF

This paper presents a sixth-order continuous-time bandpass sigma-delta modulator (SDM) for analog-to-digital conversion of intermediate-frequency signals. An important aspect in the design of this SDM is the stability analysis using the describing function method. The key to the analysis is the extension of the linear gain model for the sampled quantizer with a phase uncertainty. The single-loop, one-bit SDM is tuned at 10.7 MHz, is sampled at 40 MHz, and achieves 67-dB signal-to-(noise+distortion) ratio in 200 kHz and 80 dB in 9 kHz. The third order intermodulation is at -82 dBc for a -13-dBFS input level. The 0.5-µm CMOS chip occupies 0.9×0.4 mm2 and consumes 60 mW at 3.3 V (digital) and 5.0 V (analog). The sample frequency is variable and can be set from 30 to 80 MH