Development of gallium nitride power transistors

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2011."November 2010." Cataloged from PDF version of thesis.Includes bibliographical references (p. 78-79).GaN-based high-voltage transistors have outstanding properties for the development of ultra-high efficiency and compact power electronics. This thesis describes a new process technology for the fabrication of GaN power devices optimized for their use in efficient power distribution systems in computer micro-processors. An existing process flow was used to fabricate the baseline single-finger transistors and additional process steps were developed and optimized to fabricate multi-finger devices with total gate widths up to 12mm. These transistors offer the current and on-resistance levels required by future GaN-based power converters. Transistors with various gate widths were fabricated and characterized by DC and capacitancevoltage measurements to study how the main transistor metrics scale with gate width.by Daniel Piedra.M.Eng

Design-space and scalable technology for GaN based power transistors

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.Cataloged from PDF version of thesis.Includes bibliographical references.As silicon devices approach their intrinsic material and technological limit, there is an opportunity for alternative semiconductor materials to push the performance of electronics forward. Gallium nitride (GaN) has demonstrated very promising performance for advanced electronics, but there is still room for improvement. This thesis discusses several new transistor designs to improve the performance of GaN-based power devices as well as demonstrations of their scaling potential and integration capability with silicon. Specifically, we have developed a wide-periphery GaN fin-based high electron mobility transistor process for power switching. The process was developed with emphasis on the passivation, field plates, gate periphery scaling, and packaging. A CMOS compatible GaN processing technology on 200-mm wafers was developed and optimized, with particular attention focused on the recess etching through the wide-bandgap AlGaN barrier to reduce the contact resistance. A study of a heterogeneous integration technology to integrate GaN and Si devices was conducted. This involved an approach to monolithically integrate GaN and Si devices which used a bonded SOI wafer with a Si (111) substrate and Si (100) device layer with windows opened to access the (111) layer to selectively grow GaN. Characterization of the transistor properties in GaN windows of different sizes was performed to qualify the optimal window size for power devices in future integrated systems.by Daniel Piedra.Ph. D