IRIS RECOGNITION OPTIMIZED BY ICA USING PARALLEL CAT SWARM OPTIMIZATION

ABSTRACT Feature selection is an optimization technique used in Iris recognition technology. For producing the most accurate recognition of iris from the database, feature selection removes the unrelated, noisy and unwanted data. Parallel Cat Swarm Optimization Algorithm is one of the latest optimization algorithms in the nature league based algorithm. Its enhancement results are better than the PSO and CSO optimization algorithms. The proposal of applying the Parallel Cat Swarm algorithm is mainly used for feature selection in the process of Iris recognition. For human identification iris can be used as it is an integral part of the human body. Biometric iris recognition system compares the two iris images and produces a matching score to determine their degree of equality or inequality. Eyelid and eyelash are considered to be the unwanted parts of the eye apart from iris. By using Structure Tensor Analysis we can mask the unwanted parts of iris by taking the iris as region of interest. By using Independent Component Analysis, we can extract the texture feature in the iris from the eye. The best features are then selected using Parallel Cat Swarm algorithm from the extracted texture features. For identification purpose we need to compare the best feature with a number of features of various individuals in the database

Research Article Fault Tolerant Design for Magnetic Memories

Abstract: This study presents a Fault Tolerant memory cores based on the property of Component Reusability, a method for Fault Tolerance for content addressable memories. The memories used in the design are 256, 512, 1024 and 2048 bytes. The fault is injected into the circuitry operation by using Automatic Test Pattern Generators (ATPGs). The design has been implemented in Cadence 90 nm technology and tested with Fault Injection Circuits and ATPG effectiveness was found out to be 100% at a frequency of 500 MHZ

Low Jitter ADPLL based Clock Generator for High Speed SoC Applications

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications