The Next Generation of Internetworking

This paper describes a research effort concerned with the design of the next generation of internet architecture, which has been necessitated by two emerging trends. First, there will be at least a few orders of magnitude increase in data rates of communication networks in the next few years. For example, researchers are already prototyping networks with data rates of up to a few hundred Mbps, and are planning networks with data rates up to a few Gbps. Second, researchers from all disciplines of science, engineering, and humanities plan to use the communication infrastructure to access widely distributed resources in order to solve bigger and more complex problems. These trends provide new challenges and opportunities to researchers in the communication field. One such challenge is the design of what we call the very high speed internet (VHSI) abstraction which can help efficiently support guaranteed levels of performance for a variety of applications, and can cope with the ever increasing diversity of underlying networks with rapidly growing user population and needs. Our strategy towards achieving this ambitious goal comprises the following: • Design, specification, and prototype implementation of novel multipoint congram-oriented service that can work well with connection-oriented and datagram high speed networks, can provide variable grade service on a need basis to its applications, and can provide adequate reconfigurability to deal with survivability requirements due to network failures. • Design and implementation of gateway architecture than can support data rates of a few hundred Mbps, can interface with diverse networks, and can implement the congram-oriented service without becoming a performance bottleneck. • Development of analytical and simulation models to evaluate important tradeoffs associated with the design of a congram-oriented protocol, the resource management on diverse networks, and the design of new gateway architectures

Design of an ATM-FDDI Gateway

Asynchronous transfer mode (ATM) networks are capable of supporting a wide variety of applications with varying data rates. FDDI networks offer to support similar applications in the LAN environment. Both these networks are characterized by high data rates, low error rates, and are capable of providing performance guarantees. In this paper we present the design of an ATM-FDDI gateway that can provide high performance internetworking between these two important classes of networks. An important part of the gateway design philosophy is to partition the functionality into critical and non-critical paths. The critical path consists of per packet processing and is implemented in hardware. The non-critical path consists of connection, resource, and route management, and is implemented in software

An Overview of Segment Streaming for Efficient Pipelined Televisualization

The importance of scientific visualization for both science and engineering endeavors has been well recognized. Televisualization becomes necessary because of the physical distribution of data, computation resources, and users invovled in the visualization process. However, televisualization is not adequately supported by existing communication protocols. We believe that a pielined televisualization model (PTV) is suitable for efficient implementation of most visualization applications. In order to support this model over high speed networks, we are developing a segment streaming interprocess communication (IPC) mechanism within the Axon communication architecture. Important aspects of this development include: the segment streaming paradigm which supports low-overhead communication as well as concurrency between the communication and local computation; a two-level flow control method for distributed pipeline synchronization; and an application-oriented error control method which allows error control to be optimized for different applications. This paper describes a set of ideas that lead to the design of this IPC mechanism

Axon: Application-Oriented Lightweight Transport Protocol Design

This paper describes the application-oriented lightweight transport protocol for object transfer (ALTP-OT) in the Axon host communication architecture for distributed applications. The Axon Project is investigating an integrated design of host architecture, operating systems, and communication protocols to allow the utilization of the high band-width provided by the next generation of communication networks. ALTP-OT provides the end-to-end transport of segment and message objects for interprocess communication across a very high speed internetwork, supporting demanding applications such as scientific visualization and imaging. ALTP-OT uses rate-based flow control specifically oriented to the transfer of objects directly between application memory spaces. This document is intended to present the design of ALTP-OT, rather than serve as a complete specification and implementation report. It should be treated as a request for comments, and will be periodically updated to reflect comments form the research community and progress on Axon design and prototype implementation. Last revision April 5, 1990

Performance Analysis of the Ethernet under Conditions of Bursty Traffic

In this paper we present a simulation study of the Ethernet performance under conditions of bursty traffic. This study is motivated by two observations: Ethernet will continue to be a widely used Local Area Network (LAN), especially as an access LAN for future high speed internet (or Broadband ISDN); and future high speed applications can best be modeled as bursty sources. Bursty traffic in this study is specified using three parameters: peak bandwidth, average bandwidth, and burst factor. The simulation study shows that the inherent behavior of the Ethernet does not change with bursty traffic. That is, as long as the utilization is less than a threshold value, packet delay, is almost equal to transmission time, queue lengths are minimal, and packet delay, queue lengths, and packet loss rate increase very quickly. Although the basic trend of the Ethernet performance is the same, performance metrics deteriorate faster with bursty traffic. For example, packet loss due to collision, packet delay, and buffer sizes increase with burstiness of traffic sources. The ratio of peak to average bandwidth of traffic sources has an unexpected effect on the packet loss rate and queue lengths. At high utilization, packet loss and queue lengths are less for higher peak-to-average ratio of bursty sources

Axon Host-Network Interface Architecture for Gigabit Communication

This paper describes the design of the Axon host-network interface architecture, and performance factors determining its design. The Axon project is investigating an integrated design of the host architecture, operating systems, and communications protocols to allow applications to utilise the high bandwidth provided by the next generation of communications networks. The Axon host architecture and network interface is designed to provide a path directly between the network interface with direct access to host memory, capable of delivering bandwidth in excess of 1 Gbps to applications. This provide the ability to support demanding applications such as scientific visualisation and imaging

Specification of a Multipoint Congram-Oriented High Performance Internet Protocol

We have proposed a very high speed internet (VHSI) abstraction that can provide a variable grade service with performance guarantees on top of diverse networks. An important component of the VHSI abstraction is a novel Multipoint Congram-oriented High Performance Internet Protocol (MCHIP). Features of this protocol include support for multipoint communication, the congram as the service primitive which incorporates strengths of both connection and datagram approaches, ability to provide variable grade of service with performance guarantees, and suitability for high speed implementation. This document introduces the VHSI abstraction and then focuses on the description of MCHIP. The protocol description includes packet types, sequence of packet exchange, and representative scenarios

Axon: A High Speed Communication Architecture for Distributed Applications

There are two complementary trends in the computer and communication fields. Increasing processor power and memory availability allow more demanding applications, such as scientific visualization and imaging. Advances in network performance and functionality have the potential for supporting programs requiring high bandwidth and predictable performance. However, the bottleneck in increasingly in the host-network interface, and thus the ability to deliver high performance communication capability to applications has not kept up with the advances in computer and network speed. We have proposed a new architecture that meets these challenges called Axon, whose novel aspects include: an integrated design of hardware, operating systems, and communications protocols, stressing both performance and the required functionality for demanding applications; the proper division of hardware and software function; and reorganization of end-to-end protocols to take advantage of the increased functionality of the emerging high speed internetworks

Universal Continuous Media I/O: Design and Implementation

The problem this paper addresses is how to modify an existing operating system\u27s I/O subsystem to support new high-speed networks and high-bandwidth multimedia applications that will play an important role in future computing environments. The proposed I/O subsystem is called universal continuous media I/O (UCM I/O). This paper will cover the preliminary design of UCM I/O, some of the trade-offs and issues that need to be addressed in order to implement UCM I/O, and a summary of work in progress