Modeling and Detection of Hotspot in Shaded Photovoltaic Cells

In this paper, we address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hotspot condition. In case of shading, PV cells may experience a dramatic temperature increase, with consequent reduction of the provided power. Our model has been validated against experimental data, and has highlighted a counter-intuitive PV cell behavior, that should be considered to improve the energy efficiency of PV arrays. Then, we propose a hotspot detection scheme, enabling to identify the PV module that is under hotspot condition. Such a scheme can be used to avoid the permanent damage of the cells under hotspot, thus their drawback on the power efficiency of the entire PV system

Low Cost NBTI Degradation Detection and Masking Approaches

Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming a great concern for current and future CMOS technology. In this paper, we propose two monitoring and masking approaches that detect late transitions due to NBTI degradation in the combinational part of critical data paths and guarantee the correctness of the provided output data by adapting the clock frequency. Compared to recently proposed alternative solutions, one of our approaches (denoted as Low Area and Power (LAP) approach) requires lower area overhead and lower, or comparable, power consumption, while exhibiting the same impact on system performance, while the other proposed approach (denoted as High Performance (HP) approach) allows us to reduce the impact on system performance, at the cost of some increase in area and power consumption

Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST

During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as Low-Cost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar AF in the scan chains at capture (approximately 90% lower than conventional scan-based LBIST), while requiring a significantly lower test time (approximately 4.87 times on average lower number of test vectors) and comparable area overhead (of approximately 1.9% on average)

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC

Effect of Learning to Use a Mobility Aid on Gait and Cognitive Demands in People with Mild to Moderate Alzheimer\u27s Disease: Part I - Cane

BACKGROUND: People with Alzheimer\u27s disease (AD) exhibit balance and walking impairments that increase falls risk. Prescription of a mobility aid is done to improve stability, yet also requires increased cognitive resources. Single-point canes require unique motor sequencing for safe use. The effect of learning to use a single-point cane has not been evaluated in people with AD. OBJECTIVES: In people with AD and healthy adult controls: 1) examine changes in gait while using a cane under various walking conditions; and 2) determine the cognitive and gait costs associated with concurrent cane walking while multi-tasking. METHODS: Seventeen participants with AD (age 82.1±5.6 years) and 25 healthy controls (age 70.8±14.1 years) walked using a single-point cane in a straight (6 meter) and a complex (Figure of 8) path under three conditions: single-task (no aid), dual-task (walking with aid), and multi-task (walking with aid while counting backwards by ones). Velocity and stride time variability were recorded with accelerometers. RESULTS: Gait velocity significantly slowed for both groups in all conditions and stride time variability was greater in the AD group. Overall, multi-tasking produced a decrease in gait and cognitive demands for both groups, with more people with AD self-prioritizing the cognitive task over the gait task. CONCLUSION: Learning to use a cane demands cognitive resources that lead to detrimental changes in velocity and stride time variability. This was most pronounced in people with mild to moderate AD. Future research needs to investigate the effects of mobility aid training on gait performance

Effect of Learning to Use a Mobility Aid on Gait and Cognitive Demands in People with Mild to Moderate Alzheimer\u27s Disease: Part II - 4-Wheeled Walker.

BACKGROUND: Cognitive deficits and gait problems are common and progressive in Alzheimer\u27s disease (AD). Prescription of a 4-wheeled walker is a common intervention to improve stability and independence, yet can be associated with an increased falls risk. OBJECTIVES: 1) To examine changes in spatial-temporal gait parameters while using a 4-wheeled walker under different walking conditions, and 2) to determine the cognitive and gait task costs of walking with the aid in adults with AD and healthy older adults. METHODS: Twenty participants with AD (age 79.1±7.1 years) and 22 controls (age 68.5±10.7 years) walked using a 4-wheeled walker in a straight (6 m) and Figure of 8 path under three task conditions: single-task (no aid), dual-task (walking with aid), and multi-task (walking with aid while counting backwards by ones). RESULTS: Gait velocity was statistically slower in adults with AD than the controls across all conditions (all p values CONCLUSION: Learning to use a 4-wheeled walker is cognitively demanding and any additional tasks increases the demands, further adversely affecting gait. The increased cognitive demands result in a decrease in gait velocity that is greatest in adults with AD. Future research needs to investigate the effects of mobility aid training on gait performance

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%