Whole mitochondrial genome sequencing provides new insights into the phylogeography of loggerhead turtles (Caretta caretta) in the Mediterranean Sea

Population structure and phylogeography of the loggerhead sea turtle (Caretta caretta) have so far been assessed mainly by mitochondrial DNA (mtDNA) single-gene sequencing studies. However, phylogenetic relationships amongst matrilines, genetic characterisation of rookeries and mixed-stock analyses have suffered from the limited resolution obtained by comparison of relatively short sequences such as from the mtDNA control region. Whole mitogenome sequencing can significantly improve population genetics, particularly in marine organisms showing female natal philopatry. Despite mitogenomics becoming increasingly common in biodiversity monitoring and conservation, only a few complete mitogenomes are available for C. caretta. In this study, we sequenced the complete mtDNA of 61 loggerhead turtles sampled between 2008 and 2021 along the Italian coastline and central Mediterranean Sea. We assigned complete mtDNA haplotypes to dead embryos and bycatch samples, and introduced a first nomenclature for loggerhead mitogenomes. Analysis of mtDNA diversity, Maximum Parsimony and Bayesian phylogenetic reconstruction allowed improved resolution of lineages with respect to studies reporting on partial mtDNA control region sequence comparisons, and we were able to further inform previous analyses on loggerhead ancestry based on control region haplogroups. Overall, whole mitogenome analysis has potential for considerable improvement of evolutionary history and phylogeographic investigations as well as mixed-stock surveys of loggerhead turtles

Tunable Floating-Point for Artificial Neural Networks

Approximate computing has emerged as a promising approach to energy-efficient design of digital systems in many domains such as digital signal processing, robotics, and machine learning. Numerous studies report that employing different data formats in Deep Neural Networks (DNNs), the dominant Machine Learning approach, could allow substantial improvements in power efficiency considering an acceptable quality for results. In this work, the application of Tunable Floating-Point (TFP) precision to DNN is presented. In TFP different precisions for different operations can be set by selecting a specific number of bits for significand and exponent in the floating-point representation. Flexibility in tuning the precision of given layers of the neural network may result in a more power efficient computation. \ua9 2018 IEEE

Residue number system for low-power DSP applications

In previous works ([1]-[8]) we performed different experiments implementing FIR filtering structures. Each filter was implemented using both the Two's Complement System (TCS) and the Residue Number System (RNS) number representations. The comparison of these two implementations allows to conclude that, for these applications, the RNS uses less power than the TCS counterpart. The aim of the present paper is to highlight the reasons of this power consumption reduction. © 2007 IEEE

Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation

The development of embedded and real-time systems for Machine Learning data processing is challenging (e.g. IoT). Low latency, low power consumption and reduced hardware complexity should be the characteristics of such systems. Considering prosthetic applications, which are error-tolerant, a technique that tunes the precision of operands and operations has been chosen for a Machine Learning algorithm used for tactile data processing. This paper presents the implementation of a Tunable Floating-Point (TFP) representation into a Singular-Value Decomposition (SVD) algorithm based on the One-Sided Jacobi method. The TFP representations demonstrate high performance and efficiency improvements of the SVD algorithm. \ua9 2018 IEEE

Reducing power dissipation in pipelined accumulators

Fast accumulation is required for units such as Direct Digital Frequency Syntehesis (DDFS) processors which, together with a digital to analog converter, generate periodic waveforms. In these units, waveforms with high frequency resolution are obtained if the clocking frequency of the digital processor is high (GHz range in today's technologies). Accumulators necessary for DDFS are then deeply pipelined down to the bit-level with two main consequences: high power dissipation, due to the large number of latches/flip-flops, and large latency dependent on the granularity of the applied pipelining. In this work, we address the two issues of reducing the power dissipation in the accumulator by applying selective clock gating, and reducing the accumulation latency by pipelining the adder to adapt the delay of the carry-chain to the necessary clock period. © 2008 IEEE