Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation

Design techniques for xilinx virtex FPGA configuration memory scrubbers

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers

A Web-based Environment Providing Remote Access to FPGA Platforms for Teaching Digital Hardware Design

In this work we present the design and implementation of a Web-based application for remote access to the FPGA boards in a Digital Design Laboratory. It enables students from specialization courses to afford the design exercises at any place and time, even at home, just with an Internet access and a Web browser. At the same time, it opens the possibility of prototyping small designs to the rest of students which have no access rights to the physical Laboratory

Docencia Semipresencial en Laboratorios Docentes para Diseño de Hardware Digital en la ETSIT-UPM

En esta comunicación se describe el planteamiento seguido en la ETSIT-UPM (Escuela Técnica Superior de Ingenieros de Telecomunicación – Universidad Politécnica de Madrid) para la formación de sus alumnos en diseño de hardware digital, y la utilidad que tiene el trabajo práctico con herramientas reales y sistemas de prototipado en cada una de sus etapas. A continuación, se detalla la aproximación seguida en nuestra Escuela para posibilitar el acceso de un mayor número de alumnos a los recursos de laboratorio mediante el empleo de las TIC (Tecnologías de la Información y las Comunicaciones). El objetivo final del trabajo desarrollado es dotar a los alumnos de la capacidad para acceder de forma remota a herramientas software de desarrollo y, especialmente, a plataformas de prototipado reales, todas ellas destinadas al diseño de hardware digital. Finalmente, se introducen algunos detalles técnicos relativos a una parte fundamental del desarrollo, que es la aplicación Web para el acceso remoto a las placas de prototipado- In this paper we describe the approach taken at ETSIT-UPM (School for Telecommunication Engineers – Technical University of Madrid) to teach digital hardware design, together with the possibilities of practising with real software tools and prototyping platforms. Next, we detail our approach to facilitate access to the hardware laboratory to a greater number of students by means of TIC (Information and Communication Technologies). The final goal of our work is providing students with remote access to software development tools and prototyping platforms, all of them devoted to digital hardware design. Finally, we describe some technical details of the Web application providing remote access to the prototyping boards

Design of an Efficient Interconnection Network of Temperature Sensors

Temperature has become a first class design constraint because high temperatures adversely affect circuit reliability, static power and degrade the performance. In this scenario, thermal characterization of ICs and on-chip temperature monitoring represent fundamental tasks in electronic design. In this work, we analyze the features that an interconnection network of temperature sensors must fulfill. Departing from the network topology, we continue with the proposal of a very light-weight network architecture based on digitalization resource sharing. Our proposal supposes a 16% improvement in area and power consumption compared to traditional approache

A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration

Temperature Sensor Placement Including Routing Overhead and Sampling Inaccuracies

Dynamic thermal management techniques require a collection of on-chip thermal sensors that imply a significant area and power overhead. Finding the optimum number of temperature monitors and their location on the chip surface to optimize accuracy is an NP-hard problem. In this work we improve the modeling of the problem by including area, power and networking constraints along with the consideration of three inaccuracy terms: spatial errors, sampling rate errors and monitor-inherent errors. The problem is solved by the simulated annealing algorithm. We apply the algorithm to a test case employing three different types of monitors to highlight the importance of the different metrics. Finally we present a case study of the Alpha 21364 processor under two different constraint scenarios