21 research outputs found

    Extraction of SPICE-Type Equivalent Circuits of Signal Via Transitions using the PEEC Method

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    Digital devices and discontinuities are typically analyzed by inserting their equivalent circuits into SPICE-type simulators. The partial element equivalent circuit method has been proven to be very useful for electromagnetic modeling. It can be used in both the time and the frequency domain. In this paper, the PEEC technique is employed as an efficient full-wave modeling tool to derive SPICE-type equivalent circuits of signal via transition structures. A nodal analysis technique is utilized in conjunction with the optimization algorithm to extract the equivalent circuits, whose component values are the parameters optimized. The good agreement between different approaches demonstrates that the proposed approach can be a powerful tool for deriving the equivalent circuits of signal via transitions

    Estimating DC Power Bus Noise

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    Simultaneous switching noise (SSN) resulting from IC devices can result in significant power bus noise, as well as radiation problems. An approach for estimating the power bus noise spectrum is presented in this paper. The power bus noise caused by digital circuits injecting high-frequency noise onto the DC buses feeding digital devices is calculated. The transient current drawn by an IC device is modeled using the load current and the shoot-through current through the power dissipation capacitance. Modeling and experimental results for several digital chips are shown. The modeling agrees well with the experimental results

    An Efficient Approach for Power Delivery Network Design with Closed-Form Expressions for Parasitic Interconnect Inductances

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    Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it. Full-wave methods are often employed to study the power integrity problem. While full-wave methods can be accurate, they are time and memory consuming. The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network. However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency. A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes. Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced. Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network. While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes. Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived. This allows both frequency and transient responses to be done with SPICE simulation

    Effects of Open Stubs Associated with Plated Through-Hole Vias in Backpanel Designs

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    Plated through-hole (PTH) vias are commonly used in printed circuit boards. They usually leave open stubs if the signal(s) does not transition the entire depth of the board. These open stubs can have a negative impact on signal transmission. This summary reports the investigation of the impact of the open via stubs in a typical backpanel design

    Circuit model extraction in digital and RD circuits using the partial element equivalent circuit (PEEC) method

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    This dissertation discusses four topics relevant to power integrity and design, numerical modeling, and characterization and modeling of MEMS switches --Abstract, page iv

    Efficient Capacitance Calculations for PEEC Circuit Analysis

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    The partial element equivalent circuit (PEEC) method has proven to be useful for electromagnetic modeling. It can be used in both the time and the frequency domain. It is very important for the partial element equivalent circuit method to evaluate the partial inductances and the coefficients of potential rapidly and accurately. The evaluation of these parameters is much more challenging for the nonorthogonal mesh case. Based on a derivation for the potential due to a distribution of sources on a flat quadrilateral panel, this paper proposes an approach to rapidly extract the partial capacitance of generally quadrilateral PEEC elements. The proposed approach is compared to rectangular-shaped elements for which an analytical solution is known. The accuracy of the results demonstrates the effectiveness of the proposed approach

    Memory DIMM DC Power Distribution Analysis and Design

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    DC power bus design is critical in meeting signal integrity (SI) and electromagnetic compatibility (EMC) requirements. A suitable modeling tool is beneficial to evaluate power bus design and develop design guidelines. This paper discusses difficulties met in evaluating the power distribution design on a dual inline memory module (DIMM) board, such as a power bus with arbitrary shape, parasitic inductance associated with vias, and so on. Moreover, some solutions are given in this paper. A simple cavity model with a segmentation method was employed to model a power bus with irregular shapes. The partial element equivalent circuit (PEEC) technique was applied to model the electrical properties of a high-speed via interconnect. For each proposed approach, the difference between the estimates and measurements demonstrates the application of these approaches in the DIMM DC power distribution analysis and design

    Influence of interface electric field on interaction between molten iron and refractory interface

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    In steel processing, electric field present at the interface between molten iron and refractory materials has important influence on erosion and clogging of the submerged entry nozzle. In this study, a voltage was applied between a droplet of molten iron and several nozzle constituent materials, while measuring the liquid/solid contact angle to quantify the effect of the voltage on interfacial wetting. At 0 V the contact angles between molten iron and graphite, Al2O3-C, and ZrO2-C substrates are 130% 136 degrees, and 128% respectively. The contact angles are reduced to 85 degrees, 88 degrees, and 103 degrees when a potential of 3 V is applied. Also, it was found that silicon atoms in the molten iron diffuse and aggregate at the interface of the two phases under an external electric field, and that the electric field promotes chemical reactions between the two phases. Mass transfer, atomic diffusion, and dissolution at solid-liquid interface are promoted by interfacial electric field, which is partially responsible for the improvement in wetting. These results provide kinetic conditions related to erosion and clogging of refractory material

    Influence of Interface Electric Field on Wettability Between Molten Iron and Submerged Entry Nozzle Interface

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    The study of submerged entry nozzle clogging dynamics mainly focuses on the interface wetting behavior. So as to understand the effect of the interface electric field on the wetting behavior between the immersion nozzle and the molten steel, electrowetting experiments and field industrial tests were performed. The results show that the wettability between the iron droplet and the nozzle constituent material can be improved by applying an electric field, and the solid-liquid wetting angle decreases with increasing voltage. There is an electric field at the interface between the submerged entry nozzle and molten steel during continuous casting, and the resulting electrowetting effect significantly changes the wetting behavior between the molten steel and the nozzle, which promotes the interaction between the two phases resulting in a large amount of deposits on the inner surface of the submerged entry nozzle, causing nozzle clogging
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