Contribution à la conception de capteurs de vision CMOS à grande dynamique

This thesis, carried out within the MEDEA + European project PICS, dealt with the design of CMOS imagers for automotive safety, security and professional broadcast applications. During this thesis, work was focused on improving the CMOS imager dynamic range while keeping minimal values for the fixed spatial noise, the power consumption and the pixel area. Several pixel architectures were investigated such as logarithmic architecture pixels, integration pixels and integration with light adaptive system. These studies resulted in the design of four CMOS imagers. Two circuits have been prototyped. The sensors performances obtained by test validate the proposed pixel architectures.Cette thèse, effectuée dans le cadre du projet Européen MEDEA+, PICS, porte sur la conception d'imageurs CMOS destinés aux applications de sécurité automobile et de surveillance. Le travail s'est focalisé sur l'amélioration de la dynamique de fonctionnement des imageurs CMOS tout en conservant des valeurs de bruit spatial fixe, une consommation et une surface de pixel minimales. Plusieurs solutions ont été explorées, les pixels à compresseur logarithmique, les pixels à temps d'intégration et les pixels intégrant une adaptation aux conditions lumineuses. Ces études ont abouties à la conception et la fabrication de quatre imageurs CMOS. Ces capteurs ont été testés et ont permis de valider les approches choisies

A High Dynamic Range CMOS Imager with a Light Adaptive System and Digital Outputs

The CMOS image sensors currently available on the market propose average performances such as: a dynamic range and a SNR about 60-70dB, a correct sensitivity (limited by the integration time and the small size of the photodiode) and a correction of the fixed pattern noise (FPN) carried out in the amplifier column. However, a lot of applications such as automobile safety or monitoring, require a greater dynamic range, often higher than 100dB to capture details at the same time in highlights and shadows of a scene.....

A 120dB CMOS imager with a light adaptive system and digital outputs

A novel CMOS image sensor architecture implementing a light adaptive system with a high dynamic range is presented. This new differential architecture of the column amplifier enables a good precision and a reduced column FPN. A 128x128 pixel array has been designed in 0.35µm, 3.3V standard technology. The pixel measures 15µx15µm and the fill factor is about 16%. The dynamic range expected is up to 120dB with a frame rate up to 30 images per second

An on-pixel FPN reduction method for a high dynamic range CMOS imager

ISBN : 978-1-4244-1125-2International audienceA high dynamic range CMOS image sensor implementing a fixed pattern noise (FPN) reduction method is presented. The high dynamic range is reach through a logarithmic architecture pixel. An on-chip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an in-pixel reference current in place of the diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel. Then a double sampling technique allows removing offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source totally inside the pixel, allowing a better precision of the FPN compensation and lower power consumption. This FPN reduction method is performed while keeping only four transistors per pixel. A 128×128 pixels test chip has been designed and fabricated in 0.35μm, 3.3V CMOS standard technology. Pixel measures 10×10.6μm2 with a fill factor of 33%. The dynamic range is up to l00dB with a frame rate up to 30 images per second and a measured FPN of 2.9%rms of the total dynamic range

A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimisation

International audienceThis paper presents a light adaptive system which allows an automatic management of the integration time value of a standard 3 transistors (3T) CMOS imager. A low resolution network of high dynamic range pixels is included in this standard CMOS sensor. This low resolution network is regularly distributed on the entire photosensitive array, and computes the average incident light information. This value allows the control system to choice the best integration time value which provides the optimal image quality. This imager has been designed in a 0.350m, 3.3V CMOS technology. The basic photosensitive block layout contains four 3T standard pixels and one non linear 2T pixel. Due to this distribution, we obtain a 3.5T per pixel. This sensor has been tested and TV video sequences show the efficiency of this very simple control system

A high dynamic range CMOS image sensor with on-chip FPN reduction method

International audienceA high dynamic range CMOS image sensor implementing an innovative fixed pattern noise (FPN) reduction method is presented. The high dynamic range is reach through a logarithmic architecture pixel. An on-chip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an in-pixel reference current in place of the diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel. Then a double sampling technique allows to remove offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source inside the pixel, allowing a better current precision and a lower power consumption. This FPN reduction method is performed while keeping only four transistors per pixel. A 128x128 pixels test chip has been designed and fabricated in 0.35µm, 3.3V CMOS standard technology. Pixel measures 10x10.6µm² with a fill factor of 33%. The dynamic range expected is up to 120dB with a frame rate up to 30 images per second and a FPN of 2.65%rms of the total dynamic range

A Standard 3.5T CMOS Imager Including a Light Adaptive System for Integration Time Optimization

ISBN :978-90-481-9964-8This paper presents a light adaptive system which allows an automatic management of the integration time value of a standard 3 transistors (3T) CMOS imager. A low resolution network of high dynamic range pixels is included in this standard CMOS sensor. This low resolution network is regularly distributed on the entire photosensitive array, and computes the average light power information. This value allows the control system to choice the optimized integration time value which provides the best image quality. This imager has been designed in a 0.35 μm, 3.3 V CMOS technology. The basic photosensitive block layout contains four 3T standard pixels and one non-linear 2T pixel. Due to this distribution, we obtain a 3.5T per pixel. This sensor has been tested and TV video sequences show the efficiency of this very simple control system

Efficiency enhancement using adaptive bias control for 60GHz power amplifier

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Common-Base/Common-Gate Millimeter-Wave Power Detectors

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A 700MHz output bandwidth, 30dB dynamic range, common-base mm-wave power detector

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