Exploiting Dual-Gate Ambipolar CNFETs for Scalable Machine Learning Classification

Ambipolar carbon nanotube based field-effect transistors (AP-CNFETs) exhibit unique electrical characteristics, such as tri-state operation and bi-directionality, enabling systems with complex and reconfigurable computing. In this paper, AP-CNFETs are used to design a mixed-signal machine learning (ML) classifier. The classifier is designed in SPICE with feature size of 15 nm and operates at 250 MHz. The system is demonstrated based on MNIST digit dataset, yielding 90% accuracy and no accuracy degradation as compared with the classification of this dataset in Python. The system also exhibits lower power consumption and smaller physical size as compared with the state-of-the-art CMOS and memristor based mixed-signal classifiers

Heterogeneous Machine Learning Circuits For Nanoscale ICs

Machine learning (ML) is widely used on-chip within many different applications to solve complex problems. While the ML based systems can be very advantageous, they consume considerable power and area. This especially is a critical concern in resource limited applications. In this work, we propose solutions at various design levels to increase the efficiency of on-chip ML systems. At the circuit level, several analog single-transistor matrix-multiplication schemes are proposed that leverage various transistor technologies (such as independent double gate FinFET, triple-well CMOS, and ambipolar carbon nanotube FETs) to enable power and area efficient multiplication under various technological constraints. With these novel schemes, two operands of the multiplication are fed into two individual transistor's input pins, resulting in output current which magnitude is proportional to the product of the input signals. To extract the key tradeoffs and parameters in design of these systems, an automation framework is proposed for fast synthesis of the systems. Finally, our state-of-the-art MAC ICs are exploited alongside CMOS volatile memories, to design a fully analog on-chip training and inference system. The analog trainer exhibits orders of magnitude higher power efficiency and speed and similar accuracy as compared with the digital training solutions

Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations

Modern power analysis attacks (PAAs) and existing countermeasures pose unique challenges on the design of simultaneously secure, power efficient, and high-performance ICs. In a typical PAA, power information is collected with a monitoring circuit connected to the compromised device. The non-typical voltage variations induced on a power distribution network (PDN) by such a malicious probing are sensed with on-chip sensors and exploited in this paper for detecting PAAs in real-time using statistical analysis. A closed-form expression for the voltage variations caused by malicious probing is provided. Guidelines with respect to the PDN characteristics and number of sensors are proposed for securing power delivery. The PAA detection system is designed in a 45-nm standard CMOS process. Based on the simulation results, a PAA on an IBM benchmarked microprocessor is detected with the accuracy of 88% with 30 on-chip sensors. Power overhead of 0.34% and 14.3% is demonstrated in, respectively, the IBM microprocessor and a typical advanced encryption standard system. In a practical cryptographic device, security sensitive PDN regions can be identified, significantly reducing the number of the on-chip sensors