Quantitative investigation of SiP and SiGe layers using HAXPES and ToF-SIMS

International audienceNowadays, “more Moore” and “more than Moore” device architectures have strongly increased the importance of novel materials thereby necessitating the availability of adequate characterization and metrology for reliable process control. For instance, the introduction of SiGe or SiP compounds used in Multi Channel Field Effect devices or raised sources and drain leads to the need for the determination of the exact composition of the resulting films. In this work, the quantification of binary materials such as SiP and SiGe has been investigated using mainly non-destructive HAXPES and ToF-SIMS. Indeed, while the main obstacle to the use of RBS is the characterization of thin films, techniques with appropriate quantification capabilities like Atom Probe Tomography and Transmission Electron Microscopy are both time consuming and suffer from a lack of sensitivity due to their highly localized analysis volume. For quantitative characterization, the conventional X-ray Photoelectron Spectroscopy (XPS) is a powerful tool. Yet, its low analysis depth remains a major limiting factor to study buried interfaces and especially in this study, since the obtained Si-based layers are oxidized in ambient conditions (or because they should be protected by metallic layers of a few nanometers). A novel lab-based hard x-ray sources (HAXPES) was used to investigate both the chemical composition at the binary material surface and the in-depth distribution of SiO2 within the layer thanks to the increase of the inelastic mean free path of electrons with increasing photon energy (Chromium Kα, hν = 5414.7 eV) [1]. To confirm the composition of the materials of interest obtained by HAXPES measurements and to calculate the adequate relative sensitive factor (RSF), the same films were characterized by ToF-SIMS. However, such as for HAXPES, Secondary Ion Mass Spectrometry (SIMS) characterization of SiP/SiGe layers often suffers from matrix effects due to the non-linear variation of ionization yields with P/Ge content. This limitation can be surpassed by analyzing reference samples, by following MCs2+ secondary ions or using the full spectrum protocol [2]. Finally, the P and Ge (Si) compositions of the secondary ion beam were calculated and compared with the reference composition as determined by X-ray Diffraction. The repeatability of the measurements and the influence of the layer oxidation were also studied. To conclude, the in-depth composition of the layers and the thickness of surface oxide were accurately evaluated by coupling the HAXPES results with ToF-SIMS.[1] O. Renault et al., Faraday Disc. 236, 288-310 (2022).[2] M. Py, et al., Rapid Commun. Mass Spectrom. 2011, 25, 629–63

Thermal Evolution of Implantation Damages in Mg-Implanted GaN Layers Grown on Si

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Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p

Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p

Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

International audienceWe present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500&deg;C for 3D sequential integration. It shows that the ION/ IOFF trade-off relies mainly on the chemical dopant introduction below the offset spacer, as the activation level obtained with thermal activation is found to be high enough. The LT device demonstrated in this work, already outperforms the literature. The active profile extraction also allows to draw guidelines for further device performance improvement: using a scaled SiCO spacer (5,5nm) allows to circumvent the negligible dopant diffusion at 500&deg;C without dynamic performance penalty due to its low-k dielectric value.</p