Novel high throughput implementation of SHA-256 hash function through pre-computation technique

Hash functions are utilized in the security layer of every communication protocol and in signature authentication schemes for electronic transactions. As time passes more sophisticated applications-that invoke a security layer-arise and address to more users-clients. This means that all these applications demand for higher throughput. In this work a pre-computation technique has been developed for optimizing SHA-256 which has already started replacing both SHA-l and MD-5. Comparing to conventional pipelined implementations of SHA-256 hash function the applied pre-computation technique leads to about 30% higher throughput with only an area penalty of approximately 9.5%

Efficient implementation of the Keyed-Hash Message Authentication Code (HMAC) using the SHA-1 hash function

In this paper an efficient implementation, in terms of performance, of the Keyed-Hash Message Authentication Code (HMAC) using the SHA-1 hash function is presented. This mechanism is used for message authentication in combination with a shared secret key. The proposed hardware implementation can be synthesized easily for a variety of FPGA and ASIC technologies. Simulation results, using commercial tools, verified the efficiency of the HMAC implementation in terms of performance and throughput Special care has been taken so that the proposed implementation doesn't introduce extra design complexity; while in parallel functionality was kept to the required levels

Temporal and system level modifications for high speed VLSI implementations of cryptographic core

Hash functions are forming a special family of cryptographic algorithms, which are applied wherever message integrity and authentication issues are critical. As time passes it seems that all applications call for higher throughput due to their rapid acceptance by the market. In this work a new technique is presented for increasing frequency and throughput of the currently most used hash function, which is SHA-1. This technique involves the application of spatial and temporal pre-computation. Comparing to conventional pipelined implementations of hash functions the proposed technique leads to an implementation with more than 75% higher throughpu

Novel technique for high-throughput and power efficient cryptographic primitives

Most of internet applications incorporate a security layer in which a hash function is found. These applications are addressing to more and more clients and thus the corresponding server accepts a great number of service requests. In order to indulge these requests the security schemes must have a high-throughput. Furthermore, due to the tendency of the market to minimize devices' size and increase their autonomy to make them portable, power issues have also to be considered as long as the client-side is concerned. In this work the parallelism (or partial unrolling) technique is presented for increasing frequency and throughput of all widely used hash functions - and those that will be used in the future- hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, and SHA-512 etc. The proposed parallelism technique leads to a 33%- 50% higher throughput comparing to the most competitive implementations and to much lower power dissipation

Case study and application of pre-computation technique for hashing cores aiming at high-throughput implementations

Hash functions are forming a special family of cryptographic algorithms, which are applied wherever message integrity and authentication issues are critical. Implementations of these functions are cryptographic primitives to the most widely used cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's. As time passes it seems that all these applications call for higher throughput due to their rapid acceptance by the market. In this work a new technique is presented for increasing frequency and throughput of all widely used hash functions - and those that will be used in the future- hash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, and SHA-512 etc. Comparing to conventional pipelined implementations of hash functions the proposed pre-computation technique leads to a 40%-25% higher throughput

A top-down design methodology for ultrahigh-performance hashing cores

Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec, and VPNs utilize hash functions, which form a special family of cryptographic algorithms. Applications that use these security schemes are becoming very popular as time goes by and this means that some of these applications call for higher throughput either due to their rapid acceptance by the market or due to their nature. In this work, a new methodology is presented for achieving high operating frequency and throughput for the implementations of all widely usedand those expected to be used in the near futurehash functions such as MD-5, SHA-1, RIPEMD (all versions), SHA-256, SHA-384, SHA-512, and so forth. In the proposed methodology, five different techniques have been developed and combined with the finest way so as to achieve the maximum performance. Compared to conventional pipelined implementations of hash functions (in FPGAs), the proposed methodology can lead even to a 160 percent throughput increase

Integration of a concurrent signature monitoring mechanism in a system-on-a-chip

In this work, an IP infrastructure is presented that provides concurrent signature monitoring to the designed System-on-a-Chip (SoC). Such mechanisms ensure application code consistency and research focus integration inside high performance processor cores. A low-cost but very effective approach is offered, which has been successfully integrated in a prototype targeting safety critical applications. The advantages of the integration of this simple unit in a SoC and its characteristics are also presented. © 2007 IEEE.ST, Atmel,Altran Technologies, Alter

Speeded up and low-powered hardware implementation of the secure hash algorithm through partial unrolling

Applications that call for data integrity and signature authentication at electronic transactions invoke cryptographic primitives like hash functions. A hash function is utilized in the security layer of every communication protocol. However, as protocols evolve and new high-performance applications appear, the throughput of hash functions seems to reach to a limit. Market is asking for new implementations with higher throughputs respecting the tendency of the market to minimize devices' size and increase their autonomy to make them portable. The existing SHA-1 Hash Function implementations (SHA-1 is common in many protocols e.g. IPSec) limit throughput to a maximum of 2 Gbps. In this paper, a new a partially unrolled implementation is presented that comes to exceed this limit improving the throughput by 53%. Power issues have also been taken in consideration, in such way that the proposed implementation can be characterized as low-power

High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications

Hash functions are special cryptographic algorithms, which are applied wherever message integrity and authentication are critical. Implementations of these functions are cryptographic primitives widely used in common cryptographic schemes and security protocols such as Internet Protocol Security (IPSec) and Virtual Private Network (VPN). In this paper, a novel FPGA implementation of the Secure Hash Algorithm 1 (SHA-1) is proposed. The proposed architecture exploits the benefits of pipeline and re-timing of execution through pre-computation of intermediate temporal values. Pipeline allows division of the calculation of the hash value in four discreet stages, corresponding to the four required rounds of the algorithm. Re-timing is based on the decomposition of the SHA-1 expression to separate information dependencies and independencies. This allows pre-computation of intermediate temporal values in parallel to the calculation of other independent values. Exploiting the information dependencies, the fundamental operational block of SHA-1 is modified so that maximum operation frequency is increased by 30% approximately with negligible area penalty compared to other academic and commercial implementations. The proposed SHA-1 hash function was prototyped and verified using a XILINX FPGA device. The implementation's characteristics are compared to alternative implementations proposed by the academia and the industry, which are available in the international IP market. The proposed implementation achieved a throughput that exceeded 2,5 Gbps, which is the highest among all similar IP cores for the targeted XILINX technology. © 2006 Springer Science + Business Media, LLC