10 research outputs found
Diminishing power dissipation by FSM state assignment
Power dissipation is becoming a critical parameter in system design. This paper concerns the low power design of synchronous FSM and the power estimation with regard to a given input sequence. For that we suggest a novel and practical approach for state assignment by means of which the average rate of register switching is reduced. The resulting code determines the register configuration and acts upon size and structure on the combinational circuit. For the evaluation of the approach we adapt a simulative power estimation procedure. Experimental results demonstrate the effectiveness of the proposed approach especially in comparison with estimations based on probabilistic models. (orig.)Available from TIB Hannover: RR 7263(96,3) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman
Layoutsynthese auf der Basis einer Spezifikation auf der algorithmischen Ebene Teilvorhaben Entwurfsmethodik: Schlussbericht. Teilvorhaben Verfahrenstest : 4. Jahresbericht 01.01.1991 - 31.12.1991
Also carried out by: Dortmund Univ. (DE). Lehrstuhl Informatik 12, ZKI Dresden (DE). Bereich 1 and Technische Hochschule Ilmenau (DE). Fachbereich Mikroelektronische SystemtechnikAvailable from TIB Hannover: F93B259+a / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman