Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell

Implementation of Multi-Resolution On-Chip AHB Bus Tracer with Real Time Lossless Compression

Abstract: An On-Chip AHB Bus Tracer is a significant infrastructure that is needed to monitor the on chip-bus signals, which is vital for debugging and performance analysis and also optimizing the SoC (System On Chip). So in this paper we implement the on-chip AHB bus tracer, that traces with different resolutions, i.e. with different signal and abstraction levels depending on the need to match with specific debug /analysis needs. In addition it allows the user to switch the resolution on-the-fly. Subsequently compression of the trace without any loss of the actual trace which when reconstructed at the analyser will remain the same. This Bus Tracer adopts three trace compression techniques to achieve high compression ratio. The On-Chip AHB bus tracer with Real-Time Compression and Dynamic Multi-Resolution was designed successfully; the RTL simulations were performed successfully along with successful synthesis using Xilinx ISE

Design and Implementation of High speed and Energy Efficient MAC using Adaptive Logic

Every digital circuit objective is to achieve MEP system i.e., minimum energy, minimum power, minimum voltage. Theseconstraints can be achieved through adaptive logic. Adaptive logic is one of the fastest and innovative logic that has been implemented in digital circuit . Adaptive logic is implemented using the combination of both Nano magnetic technology and CMOS technology . Adaptive technique works very effectively in both threshold and sub � threshold regions. Internet - of - Things (IoT) is on the threshold of a massive breakthrough. Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. Reducing voltage in the circuit results in slow operation that incurs more delay. Canary circuit have been designed for error detection and error correction approach. Canary circuit results in large delay. Adaptive logic have been designed with dual latch phase in each stage. A combination of XNOR gate and flip-flop around each stage is added for the verification of correct operation. The entire architecture was modelled using Verilog code with the help of XILINX ISE tool