395 research outputs found
Deep Neural Networks for the Recognition and Classification of Heart Murmurs Using Neuromorphic Auditory Sensors
Auscultation is one of the most used techniques for
detecting cardiovascular diseases, which is one of the main causes
of death in the world. Heart murmurs are the most common abnormal
finding when a patient visits the physician for auscultation.
These heart sounds can either be innocent, which are harmless, or
abnormal, which may be a sign of a more serious heart condition.
However, the accuracy rate of primary care physicians and expert
cardiologists when auscultating is not good enough to avoid most
of both type-I (healthy patients are sent for echocardiogram) and
type-II (pathological patients are sent home without medication or
treatment) errors made. In this paper, the authors present a novel
convolutional neural network based tool for classifying between
healthy people and pathological patients using a neuromorphic
auditory sensor for FPGA that is able to decompose the audio into
frequency bands in real time. For this purpose, different networks
have been trained with the heart murmur information contained in
heart sound recordings obtained from nine different heart sound
databases sourced from multiple research groups. These samples
are segmented and preprocessed using the neuromorphic auditory
sensor to decompose their audio information into frequency
bands and, after that, sonogram images with the same size are
generated. These images have been used to train and test different
convolutional neural network architectures. The best results
have been obtained with a modified version of the AlexNet model,
achieving 97% accuracy (specificity: 95.12%, sensitivity: 93.20%,
PhysioNet/CinC Challenge 2016 score: 0.9416). This tool could aid
cardiologists and primary care physicians in the auscultation process,
improving the decision making task and reducing type-I and
type-II errors.Ministerio de Economía y Competitividad TEC2016-77785-
Spike-based control monitoring and analysis with Address Event Representation
Neuromorphic engineering tries to mimic biological
information processing. Address-Event Representation (AER) is
a neuromorphic communication protocol for spiking neurons
between different chips. We present a new way to drive robotic
platforms using spiking neurons. We have simulated spiking
control models for DC motors, and developed a mobile robot
(Eddie) controlled only by spikes. We apply AER to the robot
control, monitoring and measuring the spike activity inside the
robot. The mobile robot is controlled by the AER-Robot tool,
and the AER information is sent to a PC using the
USBAERmini2 interface.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0
An AER-Based Actuator Interface for Controlling an Anthropomorphic Robotic Hand
Bio-Inspired and Neuro-Inspired systems or circuits are a
relatively novel approaches to solve real problems by mimicking the biology
in its efficient solutions. Robotic also tries to mimic the biology and
more particularly the human body structure and efficiency of the muscles,
bones, articulations, etc. Address-Event-Representation (AER) is
a communication protocol for transferring asynchronous events between
VLSI chips, originally developed for neuro-inspired processing systems
(for example, image processing). Such systems may consist of a complicated
hierarchical structure with many chips that transmit data among
them in real time, while performing some processing (for example, convolutions).
The information transmitted is a sequence of spikes coded using
high speed digital buses. These multi-layer and multi-chip AER systems
perform actually not only image processing, but also audio processing,
filtering, learning, locomotion, etc. This paper present an AER interface
for controlling an anthropomorphic robotic hand with a neuro-inspired
system.Unión Europea IST-2001-34124 (CAVIAR)Ministerio de Ciencia y Tecnología TIC-2003-08164-C03-0
NAVIS: Neuromorphic Auditory VISualizer Tool
This software presents diverse utilities to perform the first post-processing layer taking the neuromorphic auditory sensors (NAS) information. The used NAS implements in FPGA a cascade filters architecture, imitating the behavior of the basilar membrane and inner hair cells and working with the sound information decomposed into its frequency components as spike streams. The well-known neuromorphic hardware interface Address-Event-Representation (AER) is used to propagate auditory information out of the NAS, emulating the auditory vestibular nerve. Using the information packetized into aedat files, which are generated through the jAER software plus an AER to USB computer interface, NAVIS implements a set of graphs that allows to represent the auditory information as cochleograms, histograms, sonograms, etc. It can also split the auditory information into different sets depending on the activity level of the spike streams. The main contribution of this software tool is that it allows complex audio post-processing treatments and representations, which is a novelty for spike-based systems in the neuromorphic community and it will help neuromorphic engineers to build sets for training spiking neural networks (SNN).Ministerio de Economía y Competitividad TEC2012-37868-C04-0
A spiking neural network for real-time Spanish vowel phonemes recognition
This paper explores neuromorphic approach capabilities applied to real-time speech processing. A spiking
recognition neural network composed of three types of neurons is proposed. These neurons are based on an
integrative and fire model and are capable of recognizing auditory frequency patterns, such as vowel phonemes;
words are recognized as sequences of vowel phonemes. For demonstrating real-time operation, a complete
spiking recognition neural network has been described in VHDL for detecting certain Spanish words, and it has
been tested in a FPGA platform. This is a stand-alone and fully hardware system that allows to embed it in a
mobile system. To stimulate the network, a spiking digital-filter-based cochlea has been implemented in VHDL.
In the implementation, an Address Event Representation (AER) is used for transmitting information between
neurons.Ministerio de Economía y Competitividad TEC2012-37868-C04-02/0
Building Blocks for Spikes Signals Processing
Neuromorphic engineers study models and
implementations of systems that mimic neurons behavior in the
brain. Neuro-inspired systems commonly use spikes to
represent information. This representation has several
advantages: its robustness to noise thanks to repetition, its
continuous and analog information representation using digital
pulses, its capacity of pre-processing during transmission time,
... , Furthermore, spikes is an efficient way, found by nature, to
codify, transmit and process information. In this paper we
propose, design, and analyze neuro-inspired building blocks
that can perform spike-based analog filters used in signal
processing. We present a VHDL implementation for FPGA.
Presented building blocks take advantages of the spike rate
coded representation to perform a massively parallel processing
without complex hardware units, like floating point arithmetic
units, or a large memory. Those low requirements of hardware
allow the integration of a high number of blocks inside a FPGA,
allowing to process fully in parallel several spikes coded signals.Junta de Andalucía P06-TIC-O1417Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Synthetic retina for AER systems development
Neuromorphic engineering tries to mimic biology in
information processing. Address-Event Representation (AER) is
a neuromorphic communication protocol for spiking neurons
between different layers. AER bio-inspired image sensor are
called “retina”. This kind of sensors measure visual information
not based on frames from real life and generates corresponding
events. In this paper we provide an alternative, based on cheap
FPGA, to this image sensors that takes images provided by an
analog video source (video composite signal), digitalizes it and
generates AER streams for testing purposes.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration
In this paper, we present a HDL description of a
RAM with asymmetric port widths which allows read and
write operations with different data size. This RAM is suitable
for implementing run-time reconfigurable systems in FPGA.
The proposed RAM specification has been tested with different
target devices.Ministerio de Educación y Ciencia TEC2006-11730-C03-0
Embedding Multi-Task Address-Event- Representation Computation
Address-Event-Representation, AER, is a communication protocol that is
intended to transfer neuronal spikes between bioinspired chips. There are
several AER tools to help to develop and test AER based systems, which may
consist of a hierarchical structure with several chips that transmit spikes
among them in real-time, while performing some processing. Although these
tools reach very high bandwidth at the AER communication level, they require
the use of a personal computer to allow the higher level processing of the
event information. We propose the use of an embedded platform based on a
multi-task operating system to allow both, the AER communication and
processing without the requirement of either a laptop or a computer. In this
paper, we present and study the performance of an embedded multi-task AER
tool, connecting and programming it for processing Address-Event
information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Live demonstration: Neuro-inspired system for realtime vision tilt correction
Correcting digital images tilt needs huge quantities
of memory, high computational resources, and use to take a
considerable amount of time. This demonstration shows how a
spikes-based silicon retina dynamic vision sensor (DVS) tilt can
corrected in real time using a commercial accelerometer. DVS
output is a stream of spikes codified using the address-event
representation (AER). Event-based processing is focused on
change in real time DVS output addresses. Taking into account
this DVS feature, we present an AER based layer able to correct
in real time the DVS tilt, using a high speed algorithmic
mapping layer and introducing a minimum latency in the
system. A co-design platform (the AER-Robot platform), based
into a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller,
has been used to implement the system
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