Hybrid FeRAM/RRAM synapse circuit for on-chip inference and learning at the edge

International audienceThis paper presents an experimental demonstration of a hybrid FeRAM/RRAM synaptic circuit. The circuit incorporates Metal-Ferroelectric-Metal stacks, which exhibit native FeRAM behavior and function as RRAMs after undergoing a forming operation. By leveraging the unique advantages of FeRAMs, such as ultra-low switching energy, in combination with the non-disruptive (infinite) reading capability of RRAMs, this circuit enables efficient on-chip inference and learning at the Edge

Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p

Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p