Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration

This thesis presents the Simple Universal Parallel intERface (SuperCHIPS) protocol for high interconnect density heterogeneous system integration. This is enabled by fine pitch interconnects and dielet assembly at close proximity on interconnect fabric. Dramatic improvements in bandwidth, latency, and power are achieved through this integration scheme where small dielets (1-25 mm2) are attached to a Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-dielet spacing (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Simulated models indicate that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and cross-talk (<-15 dB) achieving data rates >10 Gbps per link. Further, the maximum current density for a given current is 30x lower in copper interconnects compared to conventional solder bumps. With fine interconnect pitches (<10 μm), this scheme can achieve >5-30x improvement in data bandwidth and >50x reduction in power compared to PCB-style integration. This scheme of system integration using a dielet based assembly method provides significant reduction in design and validation cost. Test vehicles were fabricated and experimental demonstration of the integration scheme is presented

Simple Universal Parallel Interface (SuperCHIPS) Protocol for High Performance Heterogenous System Integration

This thesis presents the Simple Universal Parallel intERface (SuperCHIPS) protocol for high interconnect density heterogeneous system integration. This is enabled by fine pitch interconnects and dielet assembly at close proximity on interconnect fabric. Dramatic improvements in bandwidth, latency, and power are achieved through this integration scheme where small dielets (1-25 mm2) are attached to a Silicon Interconnect Fabric (Si-IF) at fine interconnect pitch (2-10 μm) and short inter-dielet spacing (50-500 μm) using solderless metal-to-metal thermal compression bonding (TCB). Simulated models indicate that links in the Si-IF with short wire-lengths (<500 μm) have excellent signal transfer characteristics with low channel loss (<-2 dB) and cross-talk (<-15 dB) achieving data rates >10 Gbps per link. Further, the maximum current density for a given current is 30x lower in copper interconnects compared to conventional solder bumps. With fine interconnect pitches (<10 μm), this scheme can achieve >5-30x improvement in data bandwidth and >50x reduction in power compared to PCB-style integration. This scheme of system integration using a dielet based assembly method provides significant reduction in design and validation cost. Test vehicles were fabricated and experimental demonstration of the integration scheme is presented