Boolean Expression Diagrams

This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One is a generalized version of the BDD apply-operator while the other can exploit the structural information of the Boolean expression. This ability is demonstrated by verifying that two di erent circuit implementations of a 16-bit multiplier implement the same Boolean function. Using BEDs, this veri cation problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. Generally, BEDs are useful in applications, for example tautology checking, where the end-result as a reduced ordered BDD is small

Bounded Delay Timing Analysis of a Class of CSP Programs with Choice

We extend our technique for determining exact time separation of events in systems with just concurrency to a restricted but still useful class of systems with both choice and concurrency. Such a system is described using a CSP program (including Martin's probe operator) with the restrictions that the communication behavior is data-independent, that there is no ORcausality, and that guard selection is either completely free or mutually exclusive. Such a CSP program is transformed into a safe Petri net. Interval time delays are specified on the places of the net. The timing analysis we perform is, for all possible timed executions of the system, determine the extreme separations in time for all occurrences of specified events. We formally define this problem, propose an algorithm for its solution, and apply the algorithm to an example program. 1 Introduction There has been much work in the past decade on the synthesis of speed-independent (quasi--delayinsensitive) circuits. What we dev..

Boolean Expression Diagrams

AbstractThis paper presents a new data structure called boolean expression diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of binary decision diagrams (BDDs) which can represent any Boolean circuit in linear space. Two algorithms are described for transforming a BED into a reduced ordered BDD. One is a generalized version of the BDD apply-operator while the other can exploit the structural information of the Boolean expression. This ability is demonstrated by verifying that two different circuit implementations of a 16-bit multiplier implement the same Boolean function. Using BEDs, this verification problem is solved efficiently, while using standard BDD techniques this problem is infeasible. Generally, BEDs are useful in applications, for example tautology checking, where the end-result as a reduced ordered BDD is small. Moreover, using operators for substitution and existential quantification they allow for the verification of large hierarchical circuits

Non-stochastic Analysis of Manufacturing Systems using Timed Event Graphs

Using automated methods to analyze the temporal behavior of manufacturing systems has proven to be essential and quite beneficial

Symbolic Time Separation of Events

We extend the TSE [14] timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two main contributions are 1) an iterative algorithm which continuously narrows down the domain of interest and 2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined for a given domain. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a designer (or perhaps a synthesis tool) would often want to know. 1. Introduction This paper presents a novel approach to timing analysis based on a new paradigm we refer to as "symbolic timing verif..

Symbolic model checking of timed guarded commands using difference decision diagrams

We describe a novel methodology for analyzing timed systems symbolically. Given a formula representing a set of states, we describe how to determine a new formula that represents the set of states reachable by taking a discrete transition or by advancing time. The symbolic representations are given as formulae expressed in a simple first-order logic over difference constraints of the form x y d which can be combined with Boolean operators and existentially quantied. We also show how to symbolically determine the set of states that can reach a given set of states (i.e., a backward step), thus making it possible to verify timed ctl-formulae symbolically. The main contribution is a way of advancing time symbolically essentially by quantifying out a special variable z which is used to represent the current zero point in time. We also describe a data structure called ddds for representing difference constraint formulae, and we demonstrate the efficiency of the symbolic technique by analyzing two scheduling protocols using a ddd-based model checker

Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams

The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean Expression Diagrams (BEDs) and two algorithms for transforming a BED into a Reduced Ordered Binary Decision Diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDDs (which are canonical). Based on a large number of combinational circuits, we demonstrate that BEDs either outperform or achieve results comparable to..