Towards secure cyber-physical systems for autonomous vehicles

Cyber-Physical systems have become ubiquitous. These systems integrate different functionalities to satisfy the performance requirements and take advantage of the available processing power of multi-core systems. Safety critical applications such as autonomous vehicles or medical devices rely not only on proving correct functionality of cyber-physical systems as essential certification criteria but they must also satisfy other design constraints such as energy efficiency, low power consumption and reliability. Their need to connect to the internet have created new challenges which means addressing the security vulnerabilities has become as the first-class design concern. In this talk, first a hardware/software co-design approach for two critical tasks, real-time pedestrian and vehicle detections, which are essential in advanced driving assistance systems (ADAS) and autonomous driving systems (ADS) is presented. We use partial dynamic reconfiguration on FPGA for adaptive vehicle detection. In the second part of this talk, a system-level security-aware design approach is presented to avoid or confine the impact of security compromises on the critical components of the cyber-physical systems implemented in multiprocessor systems on chip. Our system-level security approach considers the described system architecture for a specific application and analyzes its security vulnerability based on the specified security rules to generate an impact analysis report. Then, it creates a new system architecture configuration to protect the critical components of the system by providing isolation of tasks without the need to trust a central authority at run-time for heterogeneous multiprocessor system. This approach allows safe use of shared IP with direct memory access, as well as shared libraries by regulating memory accesses and the communications between the system components

Programming and Timing Analysis of Parallel Programs on Multicores

International audienceMulticore processors provide better power-performance trade-offs compared to single-core processors. Consequently, they are rapidly penetrating market segments which are both safety critical and hard real-time in nature. However, designing time-predictable embedded applications over multicores remains a considerable challenge. This paper proposes the ForeC language for the deterministic parallel programming of embedded applications on multicores. ForeC extends C with a minimal set of constructs adopted from synchronous languages. To guarantee the worst-case performance of ForeC programs, we offer a very precise reachability- based timing analyzer. To the best of our knowledge, this is the first attempt at the efficient and deterministic parallel programming of multicores using a synchronous C-variant. Experimentation with large multicore programs revealed an average over-estimation of only 2% for the computed worst-case execution times (WCETs). By reducing our representation of the programs state-space, we reduced the analysis time for the largest program (with 43, 695 reachable states) by a factor of 342, to only 7 seconds

Performance improvement through predicated execution in VLIW machines / Morteza Biglari-Abhari.

Bibliography: leaves 136-153.xiv, 153 leaves : ill. ; 30 cm.Investigates techniques to achieve performance improvement in Very Long Instruction Word machines through predicated execution.Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 200

Adaptive Real-Time Object Detection for Autonomous Driving Systems

Accurate and reliable detection is one of the main tasks of Autonomous Driving Systems (ADS). While detecting the obstacles on the road during various environmental circumstances add to the reliability of ADS, it results in more intensive computations and more complicated systems. The stringent real-time requirements of ADS, resource constraints, and energy efficiency considerations add to the design complications. This work presents an adaptive system that detects pedestrians and vehicles in different lighting conditions on the road. We take a hardware-software co-design approach on Zynq UltraScale+ MPSoC and develop a dynamically reconfigurable ADS that employs hardware accelerators for pedestrian and vehicle detection and adapts its detection method to the environment lighting conditions. The results show that the system maintains real-time performance and achieves adaptability with minimal resource overhead

REFLIX: A Processor Core with Native Support for Control Dominated Embedded Applications

Abstract: Efficient and reliable interaction with the environment (reactivity) is a key feature for many embedded system applications. Current implementation technologies that include standard microprocessors and microcontrollers, or fully customized systems, are not ideally suited to such reactive tasks either in terms of their performance constraints or in terms of design implementation and programming. We propose a microprocessor architecture that has native Esterel-like support for reactivity, flexibility of using programs and design styles as used in Esterel programming language for reactive embedded system implementation and provides time-predictable behaviors in reaction to external events. The new processor, called REFLIX, is built around already existing processor core and exploits its flexibility in allowing customization at much higher level than usual microprocessor cores. REFLIX shows manifold improvement in speed and memory footprint in dominantly reactive applications compared to the traditional microprocessors

The ForeC Synchronous Deterministic Parallel Programming Language for Multicores

International audienceCyber-physical systems (CPSs) are embedded systems that are tightly integrated with their physical environment. The correctness of a CPS depends on the output of its computations and on the timeliness of completing the computations. This paper proposes the ForeC language for the deterministic parallel programming of CPS applications on multi-core execution platforms. ForeC's synchronous semantics is designed to greatly simplify the understanding and debugging of parallel programs. ForeC allows programmers to express many forms of parallel patterns while ensuring that programs are amenable to static timing analysis. One of ForeC's main innovation is its shared variable semantics that provides thread isolation and deterministic thread communication. Through benchmarking, we demonstrate that ForeC can achieve better parallel performance than Esterel, a widely used synchronous language for concurrent safety-critical systems, and OpenMP, a popular desktop solution for parallel programming. We demonstrate that the worst-case execution time of ForeC programs can be estimated precisely

Programmation parallèle, synchrone et déterministe de multi-coeurs avec ForeC: Langage de programmation, sémantique et génération de code

Cyber-physical systems (CPSs) are embedded systems that are tightly integrated with their physical environment. The correctness of a CPS depends on the output of its computations and on the timeliness of completing the computations. The increasing use of high-performing and low-power multi-core processors in embedded systems is pushing embedded programmers to be parallel programming experts. Parallel programming is challenging because of the skills, exper ences, and knowledge needed to avoid common parallel programming traps and pitfalls. This paper proposes the ForeC language for the deterministic, parallel, and reactive programming of embedded multi-cores. The synchronous semantics of ForeC is designed to greatly simplify the understanding and debugging of parallel programs. ForeC allows programmers to express many forms of parallel patterns while ensuring that ForeC programs can be compiled efficiently for parallel execution and be amenable to static timing analysis. ForeC’s main innovation is its shared variable semantics that provides thread isolation and deterministic thread communication. All ForeC programs are correct by construction and deadlock-free because mutual exclusion constructs are not needed. Through benchmarking, we demonstrate that ForeC can achieve better parallel performance than Esterel, a widely used synchronous language for concurrent safety-critical systems, and OpenMP, a popular desktop solution for parallel programming. We demonstrate that the worst-case execution time of ForeC programs can be estimated to a high degree of precision.Les systèmes cyber-physiques sont des systèmes embarqués qui sont très fortement couplés à leur environnement. La correction d’un tel système dépend à la fois des sorties calculées et des dates auxquelles ces sorties sont produites. L’usage croissant de processeurs haute performance multi-cœurs dans les systèmes embarqués pousse les programmeurs à devenir des experts en programmation parallèle. La programmation parallèle représente un défi en raison des compétences, de l’expérience, et des savoirs qui sont requis afin d’éviter les pièges classiques. Dans cet article, nous proposons le langage de programmation ForeC pour la programmation déterministe, parallèle et réactive des processeurs embarqués multi-cœurs. La sémantique synchrone de ForeC a été conçue pour simplifier grandement la compréhension et la mise au point des programmes parallèles. ForeC permet aux programmeurs d’exprimer de nombreuses formes de schémas parallèles tout en garantissant que les programmes ForeC peuvent être compilés efficacement pour une exécution parallèle, et que leur temps d’exécution peut être calculé statiquement. La principale innovation de ForeC réside dans la sémantique des variables partagées, qui garantit l’isolation des fils d’exécution et une communication déterministe entre les fils d’exécution. Tous les programmes ForeC sont correct par construction et sans inter-blocage car les constructions d’exclusion mutuelle ne sont pas nécessaires. Grâce à des benchmarks, nous démontrons que ForeC peut obtenir de meilleures performances parallèles qu’Esterel, un langage synchrone largement utilisé pour les systèmes concurrents à sûreté critique, ainsi qu’OpenMP, une solution utilisée classiquement pour la programmation parallèle. Nous démontrons que le temps d’exécution au pire cas des programmes ForeC peut être estimé avec un très haut degré de précision