Experimental Investigation and Modelling of the Formation Kinetics of CuInSe2-based Semiconductor Thin-Films for Solar Cell Production

Die Chalkopyrit-Halbleiter CuInSe2 bzw. Cu(In,Ga)Se2 werden als Absorbermaterialien bei der industriellen Produktion der sog. CIS-Solarzellen eingesetzt. Die stark lichtabsorbierenden Dünnschichten werden dabei im sog. Stacked-Elemental-Layer (SEL) Prozess hergestellt. Dieses Verfahren ist dadurch gekennzeichnet, dass zunächst metallische Schichtstapel und Selen durch physikalische Depositionsverfahren auf ein Substrat aufgebracht werden. Aus diesem sog. Precursor wird anschließend durch thermische Prozessierung (bis etwa 550 °C) der Halbleiterabsorber synthetisiert. In dieser Arbeit wurden die chemischen Reaktionswege bei der SEL-Synthese dieser Chalkopyrite aufgeklärt. Dazu wurden Teilsysteme des CuInSe2 bzw. Cu(In,Ga)Se2 mittels dynamischer Differenz-Kalorimetrie, Röntgendiffraktometrie und in-situ Leitfähigkeitsmessung untersucht. Darüber hinaus konnten mit Hilfe der kalorimetrischen und Leitfähigkeits-Analysen die ratenbestimmenden Schritte, d.h. die kinetischen Mechanismen, bei der Selenisierung der metallischen Schichten und der Umwandlungen binärer Indium- und Galliumselenide ermittelt werden. Diese kinetischen Analysen wurden durch thermodynamische Modelle der binären Selenide ergänzt. Die Reaktionswege und Mechanismen bei der Synthese von CuInSe2 bzw. Cu(In,Ga)Se2 im SEL-Verfahren sind im Folgenden kurz zusammengefasst: CuInSe2: Aus den metallischen Schichten entsteht zunächst eine Cu11In9-Phase, die durch Selen in einer gerichteten, von der Kinetik der Grenzfläche kontrollierten Reaktion abgebaut wird. Der dominierende Vorgang ist dabei die Herauslösung des Kupfers aus dem Cu11In9, wobei CuSe2 entsteht. Dabei wird aus der intermetallischen Verbindung Cu11In9 elementares Indium freigesetzt, welches rasch zu In4Se3 weiterreagiert. Dessen anschließende Umwandlung in InSe wird durch Keimbildungs- und Kornwachstumsprozesse bestimmt. Bei der Bildung dieser Indiumselenide wird der Selenvorrat des Precursors vollständig verbraucht, weswegen die Umwandlung des CuSe2 zu CuSe erzwungen wird. CuSe wandelt sich schließlich peritektisch in Cu(2-x)Se um. Sowohl aus CuSe als auch aus Cu(2-x)Se entsteht mit InSe im Temperaturbereich von 340-550 °C schließlich CuInSe2. Cu(In,Ga)Se2: Die intermetallischen Reaktionen im quaternären Precursor bilden evtl. Cu9Ga4 und schließlich Cu11(In,Ga)9. Diese Phase wird durch Reaktion mit Selen abgebaut, wobei sich wiederum Cu9Ga4 am Substrat anreichert. Cu9Ga4 wird schließlich unter Bildung von Cu(Ga)Se2 selenisiert, welches in GaSe und CuSe zerfällt. Erst nach Umwandlung des CuSe in Cu(2-x)Se kann der Chalkopyrit CuGaSe2 entstehen. Parallel zu diesen Reaktionen verlaufen identisch zum ternären System die Reaktionen des Indiums unter Synthese von CuInSe2. Dies bildet mit CuGaSe2 am Ende des Reaktionsprozesses die Halbleiter-Mischkristallphase Cu(In,Ga)Se2 bei Temperaturen von 430-550 °C. Zur Identifikation der kinetischen Mechanismen der einzelnen Reaktionen wurden halbquantitative numerische Modellierungen genutzt. Sie erlauben u.a. eine Vorhersage der Reaktionsraten bei beliebigen Temperatur-Zeit Verläufen des Syntheseprozesses. Mit diesen Reaktionsmodellen wurde auch der Einfluss des Precursoraufbaus auf die Synthesereaktionen und deren Reproduzierbarkeit untersucht. Damit können verschiedene Überlegungen zur Optimierung des industriellen SEL-Prozesses abgeleitet werden. Es zeigt sich, dass die Morphologie der Metallschichten des Precursors nur geringen Einfluss auf die Synthesekinetik der Absorber hat. Dagegen ist die Verteilung der Phasen in den Metallschichten des Precursors von großer Bedeutung für die Reproduzierbarkeit des SEL-Prozesses. Insbesondere sind langsam reagierende oder entnetzende Zwischenschichten zu vermeiden. Situationen, in denen verschiedene konkurrierende Reaktionen einer Phase möglich sind, führen ebenfalls nicht zu reproduzierbaren Reaktionsabläufen. Daher sollte beispielsweise im Prozess vermieden werden, dass sich Ga-reiche Phasen wie Cu9Ga4 oder elementares Ga zwischen Ga-armen Phasen und Selen befinden. Als weitere Erkenntnis konnten die Ursachen für die im SEL-Prozess auftretende Segregation des Galliums an der Rückseite des Absorbermaterials aufgeklärt werden. Die Chalkopyritsynthese läuft, wie diese Arbeit zeigt, von der Precursoroberfläche in Richtung des Substrats ab. Dabei kommt es zum einen durch eine Anreicherung des Galliums am Substrat in den metallischen Precursorschichten bereits in einem frühen Stadium des Syntheseprozesses zu einer inhomogenen Ga-Verteilung. Zum anderen verzögern verschiedene Mechanismen bei der Selenisierung des Galliums die Bildung von CuGaSe2. Somit kristallisiert erst am Ende des SEL-Prozesses, und damit an der Rückseite des Absorbers, Ga-reicher Chalkopyrit.The chalcopyrite semiconductors CuInSe2 or Cu(In,Ga)Se2 are used as an absorber material for the industrial production of the so-called CIS solar cells. The thin-films are manufactured by the so-called stacked-elemental-layer (SEL) process. This technique is characterized by the physical deposition of metallic layers and selenium on a substrate. From this so-called precursor the semiconducting absorber is then synthesized by thermal processing (up to about 550 °C). In this work the chemical reaction pathways of the SEL-synthesis of these chalcopyrites were determined. For this purpose subsystems of CuInSe2 and Cu(In,Ga)Se2, respectively, were examined by dynamic scanning calorimetry, X-ray diffraction and in-situ conductivity measurements. Moreover, the rate-controlling reaction steps, i.e. the kinetic mechanisms, of the selenization of the metallic thin-films and the transformations of binary indium- and gallium-selenides could be determined by these calorimetric and conductivity measurements. These kinetic analyses were complemented by thermodynamic models of the binary selenides. The chemical reaction pathways and mechanisms of the synthesis of CuInSe2 and Cu(In,Ga)Se2, respectively, by the SEL method are summarized below: CuInSe2: First, from the metallic thin-films a Cu11In9 phase is formed, which is decomposed by selenium in a directional process kinetically controlled by a phase boundary reaction. The extraction of the Cu-atoms from the Cu11In9 crystal structure and the formation of CuSe2 dominate this process. Thereby the intermetallic compound Cu11In9 releases elemental Indium which quickly forms In4Se3. Its subsequent transformation into InSe is kinetically controlled by nucleation and growth processes. By the formation of the indium selenides the selenium supply of the precursor is completely consumed which forces CuSe2 to transform into CuSe. This phase decomposes peritectically into Cu(2-x)Se. Together with InSe, CuSe as well as Cu(2-x)Se finally synthesize CuInSe2 at temperatures of 340-550 °C. Cu(In,Ga)Se2: The intermetallic reactions in the quaternary precursor eventually form Cu9Ga4 and finally Cu11(In,Ga)9. Latter phase is decomposed by a reaction with selenium, during which Cu9Ga4 is again accumulated at the substrate. Cu9Ga4 is finally selenized forming Cu(Ga)Se2, which decomposes to GaSe and CuSe. Only after the transformation of CuSe into Cu(2-x)Se the chalcopyrite CuGaSe2 can synthesize. At the same time the reactions of the indium take place, which are identical to the ternary system and form CuInSe2. At the end of the reaction process CuInSe2, together with CuGaSe2, finally forms the solid solution phase Cu(In,Ga)Se2 at temperatures of 430-550 °C. Semiquantitative numeric models were used to identify the kinetic mechanisms of the various reactions. These models e.g. allow for a prediction of the reaction rates in arbitrary temperature-time characteristics of the synthesis process. Moreover, with these reaction models the influence of the precursor structure on the chalcopyrite synthesis reactions and their reproducibility was investigated. Several conclusions for the optimization of the industrial SEL process can be drawn. It can be seen that the morphology of the metallic precursor thin-films only has a small influence on the kinetics of the absorber synthesis. On the other hand, the distribution of the phases in the metallic precursor thin-films is crucial for the reproducibility of the SEL process. Especially slowly reacting or dewetting intermediate layers must be avoided. Situations in which a phase can participate in several competing reactions also cannot lead to reproducible reaction kinetics. Therefore it should e.g. be avoided that during the process Ga-rich phases like Cu9Ga4 or elemental Ga are situated in between Ga-poor phases and selenium. As a further result the reasons for the occurring segregation of gallium at the lower surface of the SEL-processed absorber material were clarified. As this work shows, the synthesis of the chalcopyrite in the SEL process is directional from the surface of the precursor to the substrate. Thereby, gallium already accumulates at the substrate during an early state of the thermal process, causing an inhomogeneous Ga-distribution in the metallic precursor thin-films. Second, several mechanisms during the selenization of gallium delay the formation of CuGaSe2 compared to CuInSe2. Therefore, a Ga-rich chalcopyrite can only crystallize at the very end of the SEL process, i.e. near the substrate

Step-controlled homoepitaxial growth of 4H-SiC on vicinal substrates

A comprehensive study on the step-controlled homoepitaxial growth on the (0001)Si-face of vicinal 4H-SiC substrates was performed in order to establish epitaxial growth on 2° towards <11-20> off-cut substrates and 4° towards <1-100> off-cut substrates. A standard epitaxial growth process was developed by optimizing the growth temperature T, Si/H ratio and C/Si ratio for growth on 4° towards <11-20> off-cut substrates. Thereby, step-controlled epitaxial growth was achieved within a broad operating window. The surface roughness of such epilayers varies typically between rms = 0.5 nm and rms = 2.5 nm and step-controlled growth is conserved even at a growth rate of 27 μm/h. Then, the standard growth process was applied to substrates with different off-cut angles of 2°, 4° and 8° as well as with different off-cut directions <11-20> and <1-100>. The step-controlled growth was achieved also within a wide range of Si/H ratio and C/Si ratio for growth on 8° and 4° off-cut substrates, but the process window narrows strongly for growth on 2° off-cut substrates. The epilayers surface roughness increases with decreasing off-cut angle of the substrate. Epilayers grown on 4° towards <1-100> off-cut substrates were significantly smoother than epilayers grown on 4° towards <11-20> off-cut substrates. No influence of the substrates off-cut angle and direction on the growth rate was found. The experimental results of this comprehensive study are discussed globally in consideration of other relevant publications

Modelling of effective minority carrier lifetime in 4H-SiC n-type epilayers

We present an extended model for the simulation of the effective minority carrier lifetime in 4H-SiC epiwafers after optical excitation. This multilayer model uses measured values (doping profile, point defect concentration, capture cross sections for electrons and epilayer thickness) as input parameters. The bulk lifetime and the diffusion constant are calculated from the actual time dependent excess carrier profiles, resulting in more realistic transients having different decay regimes than in other models. This enables a better understanding of optical lifetime measurements

Modelling of effective minority carrier lifetimes in 4H-SiC n-type epilayers: Poster presented at International Conference on Silicon Carbide and Related Materials, ICSCRM 2015, Giardini Naxos, Italy, October, 4th - 9th, 2015

We present an extended model for the simulation of the effective minority carrier lifetime in 4H-SiC epiwafers after optical excitation. This multilayer model uses measured values (doping profile, point defect concentration, capture cross sections for electrons and epilayer thickness) as input parameters. The bulk lifetime and the diffusion constant are calculated from the actual time dependent excess carrier profiles, resulting in more realistic transients having different decay regimes than in other models. This enables a better understanding of optical lifetime measurements

Experimental verification of the model by Klapper for 4H-SiC homoepitaxy on vicinal substrates

4H-SiC homoepitaxial layers free of basal plane dislocations (BPDs) are urgently needed to overcome the so-called bipolar degradation of high-voltage devices. BPDs being present in substrates are able to either propagate to the epilayer or convert to harmless threading edge dislocations (TEDs) in the epilayer. The model by Klapper predicts the conversion of BPDs to TEDs to be more efficient for growth on vicinal substrates with low off-cut angle. This paper aims to verify the model by Klapper by an extensive variation of epitaxial growth parameters and the substrates off-cut. It is shown that the off-cut angle is the key parameter for growth of BPD-free epilayers. Furthermore, it is shown that the model also describes adequately the behavior of different types of TEDs, i.e., TED II and TE D III dislocations, during epitaxial growth. Therefore, the model by Klapper is verified successfully for 4H-SiC homoepitaxial growth on vicinal substrates

Experimental verification of the model by Klapper for 4H-SiC homoepitaxy on vicinal substrates

4H-SiC homoepitaxial layers free of basal plane dislocations (BPDs) are urgently needed to overcome the so-called bipolar degradation of high-voltage devices. BPDs being present in substrates are able to either propagate to the epilayer or convert to harmless threading edge dislocations (TEDs) in the epilayer. The model by Klapper predicts the conversion of BPDs to TEDs to be more efficient for growth on vicinal substrates with low off-cut angle. This paper aims to verify the model by Klapper by an extensive variation of epitaxial growth parameters and the substrates' off-cut. It is shown that the off-cut angle is the key parameter for growth of BPD-free epilayers. Furthermore, it is shown that the model also describes adequately the behavior of different types of TEDs, i.e., TED II and TED III dislocations, during epitaxial growth. Therefore, the model by Klapper is verified successfully for 4H-SiC homoepitaxial growth on vicinal substrates

Improvement of 4H-SiC material quality: Invited paper presented at the First International Symposium on SiC Spintronics, Vadstena, Sweden, June 15-17, 2015

The Fraunhofer IISB will introduce its activities in Silicon Carbide to the spintronic community with a special focus on its undertakings on material development and characterization. Our activities in materials development started about 10 years ago. We were improving the 4H-SiC homoepitaxial growth process in order to avoid extended defects, e.g. dislocations and stacking faults, in homoepitaxial layers. We were able to avoid device-killing defects like Basal Plane Dislocations in epilayers and explained these experimental results by appropriate models. Within the last years, the improvement of the minority carrier lifetime by reducing the point defect density has come into focus. Therefore, the influence of epigrowth parameters like, e.g. gas mixing and growth temperature, on the point defect density and carrier lifetime are investigated by using Deep Level Transient Spectroscopy (DLTS) and microwave-detected photoconductivity decay (µ-PCD). Our recent developments target on the reduction of the carbon vacancy, which is known as a lifetime-killing defect. The experimental work is completed by implementing models regarding the point defect generation / annihilation as well as the carrier lifetime measurements. Besides the materials development, the Fraunhofer IISB has been manufacturing SiC electronic devices for more than 20 years. We are producing power electronic as well as optoelectronic SiC devices in small series or prototype fabrication. The process line could be used also to fabricate spintronic prototype devices. In our presentation, we will show and discuss ou r recent advances in materials development and characterization as well as introduce the device processing