Process Optimization and Downscaling of a Single Electron Single Dot Memory

This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices

On the imaging of electron transport in semiconductor quantum structures by scanning-gate microscopy: successes and limitations

This paper presents a brief review of scanning-gate microscopy applied to the imaging of electron transport in buried semiconductor quantum structures. After an introduction to the technique and to some of its practical issues, we summarise a selection of its successful achievements found in the literature, including our own research. The latter focuses on the imaging of GaInAs-based quantum rings both in the low magnetic field Aharonov-Bohm regime and in the high-field quantum Hall regime. Based on our own experience, we then discuss in detail some of the limitations of scanning-gate microscopy. These include possible tip induced artefacts, effects of a large bias applied to the scanning tip, as well as consequences of unwanted charge traps on the conductance maps. We emphasize how special care must be paid in interpreting these scanning-gate images.Comment: Special issue on (nano)characterization of semiconductor materials and structure

A new transport phenomenon in nanostructures: A mesoscopic analog of the Braess paradox encountered in road networks

The Braess paradox, known for traffic and other classical networks, lies in the fact that adding a new route to a congested network in an attempt to relieve congestion can counter-intuitively degrade the overall network performance. Recently, we have extended the concept of Braess paradox to semiconductor mesoscopic networks, whose transport properties are governed by quantum physics. In this paper, we demonstrate theoretically that, alike in classical systems, congestion plays a key role in the occurrence of a Braess paradox in mesoscopic networks.Comment: Invited talk at Int. Conf. on Superlattices, Nanostructures, and Nanodevices (ICSNN2012), Dresden, July 2012; submitted to Nanoscale Res. Let

Silicon single-electron memories

This paper reviews the main achievements towards the realization of memories where the information is stored by an individual electron: the so-called single-electron memories. The different routes followed are presented, ranging from multidot devices to single-dot nano-flash memories and single-electron transistor based memory cells. Finally, we illustrate the issues involved in single-electron memories by presenting a new single-dot memory device with a self-aligned nano-floating gate on top of a triangular SOI-MOSFET channel that shows persistent memory operation at room temperature.Anglai

Evidence of 2-dimensional Carrier Confinement in Thin N-channel Soi Gate-all-around (gaa) Devices

The effect of two-dimensional electron confinement is observed in thin-film, gate-all-around SOI transistors operated at low temperature. Physical 21) confinement in a thin silicon film using the silicon/gate oxide potential barrier (in contrast to heterojunction or electrostatic confinement) is shown for the first time. In these devices volume inversion gives rise to a 2DEG, and the population of the energy subbands can be controlled by the gate voltage. The position of transconductance peaks and valleys, corresponding to the population of different subbands as the gate voltage is increased, is in good agreement with theoretical predictions

SOI nano device fabrication

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Fabrication of SOI nano devices

Some current fabrication technologies of SOI nano devices are reviewed in this paper. By means of arsenic-assisted etching and oxidation effects, we have fabricated several SOI nano devices: single-electron transistor, nano floating gate memory device and cell, Ω-gate elevated source/drain MOSFET. The application of this technique for fabricating a Schottky barrier MOSFET is also presented

Structural Characterization of Graphitization Process in Pyrocarbons

A series of pyrocarbons, vapodeposited then heat treated from 1700-degrees-C up to 2800-degrees-C, was structurally characterized. Interlayer distances and mosaic spreads were measured. By analysis of the 101 and 111 bands, the graphitization rate, the domain sizes, and the graphitization process were determined. The methods, ab-initio calculations and phenomenological analyses are compared, and the physical meaning of some parameters are ascertained. The results are correlated to different types of disorder, used in the interpretation of transport properties

Nanolithographic patterning of thin metal films with a scanning probe microscope.

Using an atomic force microscope (AFM) operating in air, we locally modify thin films of e-beam-deposited Cr and Ti by applying voltage pulses between the AFM tip and the sample, which is positively biased with respect to the tip. The modifications consist in anodization and/or mechanical deformation and reach the metal/substrate interface. Metallic gates can thus be fabricated without pattern transfer. (C) 1998 Academic Press