6 research outputs found
Mapping quantum algorithms to multi-core quantum computing architectures
Current monolithic quantum computer architectures have limited scalability.
One promising approach for scaling them up is to use a modular or multi-core
architecture, in which different quantum processors (cores) are connected via
quantum and classical links. This new architectural design poses new challenges
such as the expensive inter-core communication. To reduce these movements when
executing a quantum algorithm, an efficient mapping technique is required. In
this paper, a detailed critical discussion of the quantum circuit mapping
problem for multi-core quantum computing architectures is provided. In
addition, we further explore the performance of a mapping method, which is
formulated as a partitioning over time graph problem, by performing an
architectural scalability analysis
Characterizing the spatio-temporal qubit traffic of a quantum intranet aiming at modular quantum computer architectures
Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects.Peer ReviewedPostprint (author's final draft
Scaling of multi-core quantum architectures: a communications-aware structured gap analysis
In the quest of large-scale quantum computers, multi-core distributed architectures are considered a compelling alternative to be explored. A crucial aspect in such approach is the stringent demand on communication among cores when qubits need to interact, which conditions the scalability potential of these architectures. In this work, we address the question of how the cost of the communication among cores impacts on the viability of the quantum multi-core approach. Methodologically, we consider a design space in which architectural variables (number of cores, number of qubits per core), application variables for several quantum benchmarks (number of qubits, number of gates, percentage of two-qubit gates) and inter-core communication latency are swept along with the definition of a figure of merit. This approach yields both a qualitative understanding of trends in the design space and companion dimensioning guidelines for the architecture, including optimal points, as well as quantitative answers to the question of beyond which communication performance levels the multi-core architecture pays off. Our results allow to determine the thresholds for inter-core communication latency in order for multi-core architectures to outperform single-core quantum processors.Peer ReviewedPostprint (author's final draft
On double full-stack communications-enabled architectures for multi-core quantum computers
Despite its tremendous potential, it is still unclear how quantum computing will scale to satisfy the requirements of its most powerful applications. Among other issues, there are hard limits to the number of qubits that can be integrated into a single chip. Multi-core architectures are a firm candidate for unlocking the scalability of quantum processors. Nonetheless, the vulnerability and complexity of quantum communications make this a challenging approach. A comprehensive design should imply consolidating the communications stack in the quantum computer architecture. In this paper, we explain how this vision, by entangling communications and computation in the core of the design, may help to solve the open challenges. We also summarize the first results of our application of structured design methodologies backing this vision. With our work, we hope to contribute with design guidelines that may help unleash the potential of quantum computing.Peer ReviewedPostprint (author's final draft
Mapping quantum circuits to modular architectures with QUBO
Modular quantum computing architectures are a promising alternative to
monolithic QPU (Quantum Processing Unit) designs for scaling up quantum
devices. They refer to a set of interconnected QPUs or cores consisting of
tightly coupled quantum bits that can communicate via quantum-coherent and
classical links. In multi-core architectures, it is crucial to minimize the
amount of communication between cores when executing an algorithm. Therefore,
mapping a quantum circuit onto a modular architecture involves finding an
optimal assignment of logical qubits (qubits in the quantum circuit) to
different cores with the aim to minimize the number of expensive inter-core
operations while adhering to given hardware constraints. In this paper, we
propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO)
technique to encode the problem and the solution for both qubit allocation and
inter-core communication costs in binary decision variables. To this end, the
quantum circuit is split into slices, and qubit assignment is formulated as a
graph partitioning problem for each circuit slice. The costly inter-core
communication is reduced by penalizing inter-core qubit communications. The
final solution is obtained by minimizing the overall cost across all circuit
slices. To evaluate the effectiveness of our approach, we conduct a detailed
analysis using a representative set of benchmarks having a high number of
qubits on two different multi-core architectures. Our method showed promising
results and performed exceptionally well with very dense and
highly-parallelized circuits that require on average 0.78 inter-core
communications per two-qubit gate.Comment: Submitted to IEEE QCE 202