Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI

Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de enfriamiento simulado. Para preservar los beneficios de esta solución de partida, la temperatura inicial del algoritmo de enfriamiento es seleccionada del espacio intermedio de las temperaturas. Se presentan resultados experimentales sobre diversos circuitos de prueba, demostrando que el método propuesto mejora el coste final de un 5% respecto de los resultados del programa TimberWolfSC Ver. 6.1. Es más, el tiempo de computación requerido viene a ser alrededor de un 40% menor que el empleado por TimberWolfSC Ver . 6.1

A low cost 3D vision system for positioning welding mobile robots using a FPGA prototyping system

The aim of this work is to explore some solutions for artificial vision systems applied to welding autonomous robots. We take advantage from the UNSHADES-1 system, developed in Filiation (blind for evaluation). This system can be used for building a powerful 3D vision system. The system concentrates and process the three images in parallel, producing an accurate value of the position, that can be improved if the relative position of the cameras are well defined

Selective Harmonic Mitigation Technique for High-Power Converters

In high-power applications, the maximum switching frequency is limited due to thermal losses. This leads to highly distorted output waveforms. In such applications, it is necessary to filter the output waveforms using bulky passive filtering systems. The recently presented selective harmonic mitigation pulsewidth modulation (SHMPWM) technique produces output waveforms where the harmonic distortion is limited, fulfilling specific grid codes when the number of switching angles is high enough. The related technique has been previously presented using a switching frequency that is equal to 750 Hz. In this paper, a special implementation of the SHMPWM technique optimized for very low switching frequency is studied. Experimental results obtained applying SHMPWM to a three-level neutral-point-clamped converter using a switching frequency that is equal to 350 Hz are presented. The obtained results show that the SHMPWM technique improves the results of previous selective harmonic elimination pulsewidth modulation techniques for very low switching frequencies. This fact highlights that the SHMPWM technique is very useful in high-power applications, leading its use to an important reduction of the bulky and expensive filtering elements.Ministerio de Ciencia y Tecnología TEC2006-03863Junta de Andalucía EXC/2005/TIC-117

Digital test design with an "ad hoc" strategy for an industrial ASIC with large dimension

The development of digital ASIC's with a large area states a lot of doubts when the ingenieer must design a test strategy. The design of an industrial circuit advises a test to be made quite similar to the normal field functioning. If the size of the die is large or quite complex this idea can be unreachable. The techniques of automatic test maybe relevant, thought it should be increased the cell and routing area. If the circuit has been designed with a hierarchical manner with separated blocks, or works with some precompiled megacells, the application of these techniques can be inadvisable, so that we suggest a mixed solution. In this paper we describes a set os a “ad hoc” strategies for the construction of a test for a large digital circuit, it has been introduced soma additional simple circuits able to make visible some part of the whole chip. Those ideas have been introduced in an industrial circuit which today is being manufactured

Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework

Due to the increase in size and complexity of VLSI integrated circuits, new design tools are becoming needed. Telecommunications and Electronic Industry demand designs that integrate intensive digital signal processing blocks and complex control tasks. Rapid Prototyping techniques introduce a new stage into the design flow that overcome the drawbacks of simulation stage and shorten design times. Advanced FPGAs can host the design for its emulation and can run inserted into the final system. The benefits of their use go beyond the simple rapid prototyping approach, and are able to provide additional information and other useful tasks that will be presented in this paper

HADES-1: A rapid prototyping environment based on advanced FPGA’s

Rapid prototyping of large digital systems is becoming supported with the use of new advanced FPGA's. These FPGA's can give more Information than functional simulation and emulation tasks, due to their inner inspection features. This paper presents HADES-l, a new environment for rapid prototyping and hardware debugging. HADES-l is based on one FPGA of the VIRTEX family, exploiting the advanced features of the SelectMap port and a fast link with the host PC

RAISE: A detailed routing algorithm for field-programmable gate arrays

This paper describes a new detailed routing algorithm, speciffically designed for those types of architecturesthat are found on the most recent generations of Field-Programmable Gate Arrays (FP-GAs). The algorithm, called RAISE, can be applied to a broad range of optimizations problems and has been used for detailed routing of symmetrical FPGAs, whose routing architecture consists of rows and columns of logic cells interconnected by routing channels. RAISE (Router using AadaptIve Simulated Evolution) searches not only for a possible solution, but tries to find the one with minimum delay. Excelent routing results have been obtained over a set of several benchmark circuits getting solutions close to the minimum number of tracks

OFDM synchronization scheme for Power Line Telecommunications (PLT)

This paper presents a new scheme for OFDM time and frequency synchronization with application in Power Line Telecommunications (PLT). Simulation results show an excellent behavior, even for the low values of SNR in the synchronizer input inherent to PLT. The synchronizer has been prototyped on an FPGA prior to be integrated in the single-chip PLT system