Delay and current evaluation in CMOS circuits

An accurate and fast technique has been developed for computing the supply current as well as the delay in CMOS combinational circuits. It is based on a new analytical model of the CMOS inverter which is designed specifically to compute the maximum supply current and the delay without recourse to integration. If the current waveform is needed, integration is used only for the trailing edge. This model can be used not only to compute maximum supply current and delay in CMOS circuits, but also to detect dynamic hazards.The extension to general CMOS circuits is achieved through a collapsing method which reduces each gate to an equivalent inverter. Unlike previous attempts to solve this problem, our technique is not limited to single input transitions or to step inputs. It also takes into account the relative positions of the switching inputs in series-connected transistors.The improvement in computation speed, for delay and maximum current in large circuits, approaches 4 orders of magnitude compared to HSPICE using the level-3 MOSFET model. For current waveforms the speed improvement approaches 3 orders of magnitude. The accuracy of computing the delay and the supply current is usually within 10% and 12%, respectively. Although the technique has been tested on static CMOS gate circuits, the extension to dynamic circuits is straightforward