A Study on Electrical Characterization of Nanoscale Si-MOSFETs Using RF S-parameter Measurement

DoctorAs CMOS technology has scaled down, problems such as gate leakage current density due to direct tunneling mechanism in thin oxide film and velocity saturation, and extrinsic source/drain resistance have been a roadblock for further scaling of device. And they have made evaluation of intrinsic performance challenging. To evaluate intrinsic performance of nano-scale device accurately, effect of these factors on device performance should be considered and corrected reasonably. In this thesis, a systematic study on several methods based on RF S-parameter measurement and modeling as candidate techniques for electrical characterization of the advanced MOSFETs has been performed. With the RF characterization techniques, device performance of the current state-of-the-art La (lanthanum)- incorporated Hf (hafnium) based high-k/metal gate MOSFETs has been investigated for RF operation.Potential error source in the conventional RF C-V technique using the parallel two-element equivalent circuit approximation in ultra-leaky MOS device system with a large parasitic series resistance has been analyzed In combination of gate conductance due to high gate leakage and parasitic series resistance, the capacitance extracted by conventional technique reduces 3% for SiO2 device and 13% for high-k device used in this study. The modified RF C-V technique using three-element equivalent circuit model has been developed and demonstrated as an accurate technique for capacitance extraction in a leaky MOS system. With the modified RF C-V technique, effective oxide thickness evaluation of SiO2 and high-k gate dielectric has been performed.Limitation of the conventional extraction methods of the extrinsic series resistances has been investigated. As CMOS technology has been advanced, measurement frequency required for accurate extraction of the extrinsic series resistance has become very high. Data measured at frequencies which are not high enough can generate error when series resistances are extracted by the conventional method. If the measurement frequency is lower than minimum measurement frequency, the result leads to overestimation. To overcome this limitation, a new method for RF series resistance extraction has been presented and compared with the conventional method, and is found out that the proposed method can reduce effectively measurement frequency. It is proposed that small drain voltage (e.g. 50 mV) can induce sufficiently high lateral field in era of sub-50 nm channel length, leading to underestimation of effective mobility when a conventional split C-V technique is applied. In order to reduce this lateral field effect on the extraction of effective mobility, zero-drain-bias small-signal channel conductance method based on RF modeling has been proposed. With applying it to metal/high-k CMOS with sub-50-nm gate length, short channel effect of mobility has been investigated. The effect of a La-induced dipole on the high frequency performance and characteristics of La-doped HfSiON devices has been also investigated. Essentially, dipole-induced dielectric relaxation has the same effect as a non-quasi-static effect except that it occurs at a much lower frequency than the non-quasi-static effect. Due to the dipole-induced DR, it was found that high frequency performance, especially voltage gain, severely degrades because of substantial degradation in gate capacitance, transconductance, and output resistance in a frequency range below 1 GHz

70nm CMOS BSIM4 Macro modeling for RFIC design

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A Novel Series-resistance Extraction Method for Nano-scaled nMOSFETs Considering Mobility Degradation due to Vbs

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Optimized scalable I-V Modeling for 70nm Gate length Nano-CMOS using BSIM4

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RF characteristics for 70 nm MOSFETs below 77K

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RF performance degradation in 100-nm metal gate/high-k dielectric nMOSFET by hot carrier effects

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RF degradation of short channel metal gate/high-k dielectric nMOSFET by hot carrier effect

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DC and Reliability Characteristics of 45nm Node MOSFETs with using HfSiON/TiN Gate Stacks

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Fabrication, DC and Low Frequency Noise Characteristics of Silicon Nanowire FET

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Novel Extrinsic Series Resistance Extraction Methodology for Nanoscale MOSFETs

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