A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain with Digital-Assisted DC-Offset Calibration for Ultra-Wideband

[[abstract]]A 250 MHz analog baseband chain for ultra-wideband was implemented in a 1.2 V 0.13 ¿ m CMOS process. The chip has an active area of 0.8 mm2. In the analog baseband, PGAs and filters are carried out by current-mode amplifiers to achieve wide bandwidth and wide dynamic range of gain, as well as low noise and high linearity. Besides, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers. A 6 th-order Chebyshev low-pass filter realized in Gm-C topology is designed in the baseband chain for channel selection. Digitally-assisted DC-offset calibration improves second-order distortion of the entire chain. The design achieves a maximum gain of 73 dB and a dynamic range of 82 dB. Measured noise figure is 14 dB, an IIP3 of -6 dBV, and IIP2 of -5 dBV at the maximum gain mode. The analog baseband chain consumes 56.4 mA under supply of 1.2 V.[[incitationindex]]SCI[[incitationindex]]E

An Ultra-Low Power Multi-Rate FSK Transmitter for Wireless Sensors and

[[sponsorship]]IEEK[[incitationindex]]EI[[conferencetype]]國際[[conferencedate]]20140115~20140118[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]亞庇, 馬來西

[[alternative]]Design of a Time-To-Digital Converter with Resolution of Sub-Pico Second

計畫編號：NSC100-2221-E032-066 研究期間：20110801~20120731 研究經費：463,000[[abstract]]隨著半導體製程之進步，電晶體的操作速度越來越快。相反的，電晶體的操作電壓卻 越來越低，使得以往在電壓域(Voltage Domain)設計電路變得越來越困難。尤其是在 類比數位轉換器的設計上，要達到高解析度變得十分困難。反之，由於電晶體的操作 速度越來越快，因此在時間域(Time domain)上處理訊號可達到的解析度越來越高。因 此運用時間數位轉換器處理訊號可達具有高解析度、省電、快速等優點。本計畫目的 在於發展一解析度小於1ps 之時間數位轉換器，可廣泛應用於類比數位轉換器、全數 位鎖相迴路(ADPLL)的設計上。並具有縮小晶片面積、省電等優點。[[abstract]]Advanced semiconductor process leads transistors featured high speed and low operating voltage. Low operating voltage results in difficulty of high resolution in voltage domain, especially for design of analog-to-digital converters (ADCs). On the contrary, Transistors featured high speed lead to high resolution in time domain. Therefore, the purpose of this project is to develop a time-to-digital converter (TDC) with resolution of sub-pico second applying in analog-to-digital converters (ADCs) and all-digital phase-locked loop (ADPLL). The time-to-digital converter also features low power and small chip area.[[sponsorship]]行政院國家科學委員

[[alternative]]深次微米互補式金氧半製程之寬頻射頻接收發射器設計

99學年度新聘教師論文著作[[abstract]]This dissertation presents a wideband RF transceiver for ultra-wideband (UWB) applications implemented in a 1.2 V 0.13 μm CMOS process. The receiver design focuses on mode 1 of multi-band (MB) orthogonal frequency division multiplexing (OFDM) UWB (3~5 GHz) which is defined as essential band by WiMedia Alliance. The receiver chain is composed by a broadband 3~5GHz ESD-protected low-noise amplifier, a 3th-order notch filter, a current-mode down conversion mixer and a 250MHz wideband analog baseband. In the analog baseband, PGAs and filters are carried out by current-mode amplifiers to achieve wide bandwidth and wide dynamic range of gain, as well as low noise and high linearity. Besides, a current-mode Sallen-Key low-pass filter is adopted for effective rejection of out-of-band interferers. A 6th-order Chebyshev low-pass filter realized in Gm-C topology is designed in the baseband chain for channel selection. Digitally-assisted DC-offset calibration improves second-order distortion of the entire chain. The entire receiver consumes 100 mW under a supply voltage of 1.2 V. In the design of transmitter, we attempt to cover both mode 1 and Band Group 3 of MB-OFDM UWB (3~8 GHz). The 3~8 GHz transmitter chain integrates an analog baseband, an in/quadrature-phase (IQ) modulator, a variable gain amplifier (VGA), a differential-to-single amplifier, a power amplifier, as well as a transmitted signal strength indicator (TSSI). The IQ modulator incorporates DC-offset cancellation circuits to improve carrier leakage suppression. This transmitter provides linear-in-dB output power tuning of 14 dB to fulfill the requirement of WiMedia UWB. Measured maximum output power and OP1dB are -5 dBm and +1.5 dBm, respectively. Measured carrier leakage suppression is over 40 dB after calibration. The high linearity and accurate IQ modulation lead to an error vector magnitude (EVM) of -28 dB under the data rate of 480 Mb/s in WiMedia Mode 1. The entire transmitter consumes 66 mW under a supply voltage of 1.2 V.[[abstract]]本論文描述一以1.2 V 0.13 μm CMOS 製程實現，應用於超寬頻系統之寬頻射頻接收發射器設計。接收機設計在3~5 GHz 的頻段。整個接收機是由一3~5 GHz的寬頻低雜訊放大器、三階槽口濾波器、電流式的降頻混頻器與一頻寬為250 MHz之類比基頻電路所組成。在類比基頻的電路中，可變增益放大器與濾波器利用電流式放大器的形式設計達到寬頻、高增益動態範圍、低雜訊與高線性度之特點。此外一電流式Sallen-Key 低通濾波器被設計用來有效地濾除通道外的干擾訊號。一個六階的Chebyshev 低通濾波器被設計用來提供通道選擇。一數位輔助的直流偏移校正電路用來降低整個類比基頻電路的二階諧波失真。整個接收器電路在1.2 V 的操作電壓下消耗100 mW。 在發射器的設計上，我們涵蓋3~8 GHz 的頻率範圍。整個發射器電路整合了一類比基頻電路、調變器電路、可變增益放大器、差動轉單端放大器與功率放大器，並整合了發射訊號強度指標電路。調變器電路並包括一直流偏移消除電路來增進其載波洩漏的抑制能力。整個發射器提供14 dB 的發射功率可調範圍，並具有-5 dBm的最大發射功率與+1.5 dBm 的輸出P1dB。藉由直流偏移消除電路可使得載波洩漏抑制達到40 dB。其高線性度與調變精準度使得在480 Mb/s 下EVM可達-28 dB，可滿足WiMedia Mode 1 的規格要求。整個發射器電路在1.2 V 的操作電壓下消耗66 mW

[[alternative]]Design of an Ultra-Low Power, Low-If/Zero-If Reconfigurable and Variable Data Rate Fsk Receiver

計畫編號：NSC101-2221-E032-069 研究期間：201208~201307 研究經費：732,000[[abstract]]頻率鍵移接收解調電路可廣泛應用於穿戴式或植入式生理訊號感測器與各種環境監測 之感測器上，其具有超低功率消耗與抗干擾能力強之優點，因此可大幅增加感測器之 使用壽命並提供可靠與穩定之資料傳輸品質。本計畫提出一高速、可變架構與可變傳 輸速率與超低功耗之頻率鍵移接收解調電路設計。突破先前頻率鍵移解調電路最高解 調速度為10Mb/s 之限制，傳輸速率可達20Mb/s 以上，因此可大幅降低接收每位元資 料所需之能源消耗，提高能源效率。此電路架構可根據使用需求調整其傳輸速率範圍 1Mb/s-20Mb/s，以達到功耗與傳輸速率最佳化之目的。[[abstract]]Ultra-low power (ULP) frequency shift keying (FSK) receivers can be applied for wearable/implantable physiology sensors and environment monitor sensors. Comparing to on-off keying (OOK) receivers, FSK receivers provides better immunity against interference. Therefore, a ULP FSK receiver can provide stable link quality and extend life time of sensors. In this project, we propose a high data rate, ultra-low power, Low-IF/Zero-IF Reconfigurable and variable data rate FSK receiver which can have data rate of over 20 Mbps. Thus, the energy consumption per received bit can be great reduced, which results in a great improvement in energy efficiency. Owing to variable data rate of the FSK receiver, power consumption and transmission data rate of the FSK receiver can be trade-off for optimization under different operating conditions.[[sponsorship]]行政院國家科學委員

2.5-GHz hybrid oscillator with both a wide tuning range and high frequency resolution for digital PLL

[[abstract]]A hybrid oscillator for WiMAX application is presented with comprehensive study. The hybrid oscillator is part of a digital fractional-N frequency synthesizer realized in a 0.13-um CMOS process. By operating the DAC followed by oscillator, the requirement of finest switched capacitor value and high-speed dithering of ǻӢ data converter are relaxed. A time-domain simulation approach for modeling the phase noise introduced by the frequency discretization was taken. The proposed approach is well suited to investigate complex interactions in the sophisticated system, which cannot be studied by using conventional RF and analog simulation tools. The prototype core chip consumes 8.6 mA from a 1.4-V supply while providing a phase noise of -120.35 dBc/Hz at 1 MHz offset from 2.808 GHz carrier and a 570 MHz frequency tuning range (23%).[[conferencetype]]國際[[conferencedate]]20110415~2011041

An Ultra-Low Power All-Pass Filter Implemented Tunable Phase Shifter for Mult-Rate FSK Receivers

[[sponsorship]]The institute of electronics engineers of Korea (IEEK); The institute of electronics, information, communication engineers, engineering science society (IEICE ESS); The electrical engineering/ electronics, computer, telecommunications and information association[[conferencetype]]國際[[conferencedate]]20130630~20130703[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Yeosu, Kore

[[alternative]]Wideband Current-Mode Analog Baseband Circuits for Ultra-Wideband

計畫編號：NSC99-2218-E032-007研究期間：201010~201107研究經費：424,000[[sponsorship]]行政院國家科學委員

A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process

[[abstract]]A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency multiplication. The MDLL, implemented in 90-nm CMOS technology, occupies about 1 mm2 and works at 400 MHz with multiplication ratio of 4. The complete synthesizer, including the output buffers, dissipates 31 mW from a 1.2V supply at 400 MHz. The rms jitter is 0.934 ps according to the phase noise integrated from 1 KHz to 1 MHz, when the output frequency is 400 MHz.[[conferencetype]]國際[[conferencelocation]]Athens, Greec

[[alternative]]Design of an Ultra-low Power Multi-rate FSK Transceiver

計畫編號：NSC102-2221-E032-070 研究期間：201308~201407 研究經費：759,000[[sponsorship]]行政院國家科學委員