Automotive Intrusion Detection Based on Constant CAN Message Frequencies Across Vehicle Driving Modes

The modern automobile relies on numerous electronic control units communicating over the de facto standard of the controller area network (CAN) bus. This communication network was not developed with cybersecurity in mind. Many methods based on constant time intervals between messages have been proposed to address this lack of security issue with the CAN bus. However, these existing methods may struggle to handle variable time intervals between messages during transitions of vehicle driving modes. This paper proposes a simple and cost-effective method to ensure the security of the CAN bus that is based on constant message frequencies across vehicle driving modes. This proposed method does not require any modifications on the existing CAN bus and it is designed with the intent for efficient execution in platforms with very limited computational resources. Test results with the proposed method against two different vehicles and a frequency domain analysis are also presented in the paper

An fpga implementation of decision tree classification

Data mining techniques are a rapidly emerging class of applications that have widespread use in several fields. One important problem in data mining is Classification, which is the task of assigning objects to one of several predefined categories. Among the several solutions developed, Decision Tree Classification (DTC) is a popular method that yields high accuracy while handling large datasets. However, DTC is a computationally intensive algorithm, and as data sizes increase, its running time can stretch to several hours. In this paper, we propose a hardware implementation of Decision Tree Classification. We identify the computeintensive kernel (Gini Score computation) in the algorithm, and develop a highly efficient architecture, which is further optimized by reordering the computations and by using a bitmapped data structure. Our implementation on a Xilinx Virtex-II Pro FPGA platform (with 16 Gini units) provides up to 5.58 × performance improvement over an equivalent software implementation.

Summer Engagement in Cyber Undergraduate Research Experiences (SECURE)

Background: This virtual initiative, called Summer Engagement in Cyber Undergraduate Research Experiences (SECURE), was established as a response to support students who may have lost summer internships and/or have financial hardships due to COVID-19. Several students in the program were NSF S-STEM scholars, a mix of computer engineering, cyber security engineering, electrical engineering and software engineering students.Purpose/Hypothesis: The main question addressed by this initiative was whether we could build a virtual undergraduate research experience that enabled students to apply their studies and knowledge similarly as they would in a traditional summer internship. Goals for the experience included providing small-group mentoring as well as broader opportunities for students to learn about design and research skills and to collaborate across projects.Design/Method: Sixteen paid students were assigned to one of ten projects. Several students were classified as sophomores, and others were more advanced. Projects were proposed by faculty mentors with an emphasis on the development of educational experiences using research and/or design approaches. Several projects revolved around cyber security. We introduced students to the research process, while adapting to the limitations of a virtual program. While our main goal was to support students and provide summer work, we also made progress on projects that were established before the program.Results: The SECURE program operated from May 18 through July 31, 2020. The program was funded using funds remaining in an NSF grant with the approval of the program manager. It was successfully implemented through the concerted efforts of faculty, staff and graduate students to rapidly set up program operations. The goals for the program were met, and the feedback from the students and mentors were very positive.Conclusions: We demonstrated it is possible to rapidly build a virtual internship program to meet student needs, and we are working to obtain funding to continue the project next summer. The future goal will be to offer a hybrid model where students can be virtual or a combination of virtual and on-campus

Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach

Abstract-Since its introduction over two decades ago, graphics hardware has continued to evolve to improve rendering performance and increase programmability. While most undergraduate courses in computer graphics focus on rendering algorithms and programming APIs, we have recently created an undergraduate senior elective course that focuses on graphics processing and architecture, with a strong emphasis on laboratory work targeting hardware prototyping of the 3D rendering pipeline. In this paper, we present the overall course layout and FPGA-based laboratory infrastructure, that by the end of the semester enables students to implement an OpenGL-compliant graphics processor. To our knowledge, this class is the first that takes a hardware prototyping approach to teaching computer graphics and architecture

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels

Developing high performance embedded vision applications requires balancing run-time performance with energy constraints. Given the mix of hardware accelerators that exist for embedded computer vision (e.g. multi-core CPUs, GPUs, and FPGAs), and their associated vendor optimized vision libraries, it becomes a challenge for developers to navigate this fragmented solution space. To aid with determining which embedded platform is most suitable for their application, we conduct a comprehensive benchmark of the run-time performance and energy efficiency of a wide range of vision kernels. We discuss rationales for why a given underlying hardware architecture innately performs well or poorly based on the characteristics of a range of vision kernel categories. Specifically, our study is performed for three commonly used HW accelerators for embedded vision applications: ARM57 CPU, Jetson TX2 GPU and ZCU102 FPGA, using their vendor optimized vision libraries: OpenCV, VisionWorks and xfOpenCV. Our results show that the GPU achieves an energy/frame reduction ratio of 1.1–3.2× compared to the others for simple kernels. While for more complicated kernels and complete vision pipelines, the FPGA outperforms the others with energy/frame reduction ratios of 1.2–22.3×. It is also observed that the FPGA performs increasingly better as a vision application’s pipeline complexity grows