A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition

A general model for the frequency response of multiphase charge transfer delay lines

A general model for the transfer function of a multiphase CTD delay line is presented in the z-domain. It covers the widely used single-phase transfer function. The new model has been applied for CTDs with asymmetrical potential wells. If poor charge transfer efficiencies are considered, the new model offers a significant correction to the single phase model

A CMOS four-quadrant analog multiplier

A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz

A CMOS class-AB transconductance amplifier for switched-capacitor applications

A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-rate (5 V/μs) can be obtained by applying a large bias current to the core OTA. Due to the class-AB operation of the output stage, a high output impedance can be obtained by applying a small bias current to the output stage, resulting in a high DC-gain (61.6 dB). When the performance of this class-AB OTA is compared with that of basic single-stage OTAs it is found that the output impedance of the class-AB OTA is increased without limiting the bandwidth or slew-rat

A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation

The examined class of circuits includes voltage multipliers, current multipliers, linear V-I convertors, linear I-V convertors, current squaring circuits, and current divider circuits. Typical for these circuits is an independent control of the sum as well as the difference between two gate-source voltages. As direct use is made of the basic device characteristics, only a small number of transistors is required in the presented circuits

A CMOS analog continuous-time delay line with adaptive delay-time control

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass section

A novel modification to backpropagation sample selection strategy

Random sample selection method in backpropagation results in convergence on the error (root of mean squared error, RMSE) surface. These problems, which are caused by the extreme (worst-case) errors, can be solved by a different sample selection strategy. A sample selection strategy has been proposed, which provides lower maximal errors and a higher confidence level on the expense of slightly increased RMSE. Applications are presented in the field of spectroscopic ellipsometry (SE), a sensitive, non-destructive but indirect analytical technique. Demonstrative example shows feature common to simulated annealing in the sense of escaping local minima

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW