Development of Comprehensive Devnagari Numeral and Character Database for Offline Handwritten Character Recognition

In handwritten character recognition, benchmark database plays an important role in evaluating the performance of various algorithms and the results obtained by various researchers. In Devnagari script, there is lack of such official benchmark. This paper focuses on the generation of offline benchmark database for Devnagari handwritten numerals and characters. The present work generated 5137 and 20305 isolated samples for numeral and character database, respectively, from 750 writers of all ages, sex, education, and profession. The offline sample images are stored in TIFF image format as it occupies less memory. Also, the data is presented in binary level so that memory requirement is further reduced. It will facilitate research on handwriting recognition of Devnagari script through free access to the researchers.Comment: 5 pages, 8 figures, journal pape

Characterization and Improvement of Thrust Balance Measurement Technique for SX3 Applied-Field Magnetoplasmadynamic Thruster

Steady state applied-field magnetoplasmadynamic thruster promises good compromise between thrust density and specific impulse, making them relevant for interplanetary missions requiring high thrusts. The IRS 100 kW gas-fed steady-state AF-MPD SX3 thruster has shown promising results in previous held test campaigns. Experimental results in those campaigns showed non-linear behavior of tare forces, resulting in respective error in the thrust measurement and this error then propagates in further calculation of Isp, thrust efficiency, etc. This motivated improvement in the thrust balance and measurement technique. Various error sources in the thrust measurement technique were identified and solutions to mitigate them were presented. A number of changes in the thrust balance were made in order to improve the measurement technique and data quality. The effectiveness of improvements had been experimentally characterized and presented. Previously the thrust measurement technique featured manual control of the measurement setup which led to complex and inconsistent test procedures. A new programmable electronic control unit was specifically designed for more consistent and automated measurement and calibration procedure. Potential error sources of the measurement chain have been systematically identified, characterized and discussed. The analysis tool for thrust characterization was redesigned which gives fine control of the interval selection and data export, this ensured accurate thrust and calibration calculations. The new code is more modular to adapt for changes and is very flexible with user interaction reducing complexity while still retaining the functionality. To further improve the measurements accuracy some suggestions are made.Outgoin

FPGA Implementation of Fast Fourier Transform Core Using NEDA

Transforms like DFT are a major block in communication systems such as OFDM, etc. This thesis reports architecture of a DFT core using NEDA. The advantage of the proposed architecture is that the entire transform can be implemented using adder/subtractors and shifters only, thus minimising the hardware requirement compared to other architectures. The proposed design is implemented for 16-bit data path (12–bit for comparison) considering both integer representation as well as fixed point representation, thus increasing the scope of usage. The proposed design is mapped on to Xilinx XC2VP30 FPGA, which is fabricated using 130 nm process technology. The maximum on board frequency of operation of the proposed design is 122 MHz. NEDA is one of the techniques to implement many signal processing systems that require multiply and accumulate units. FFT is one of the most employed blocks in many communication and signal processing systems. The FPGA implementation of a 16 point radix-4 complex FFT is proposed. The proposed design has improvement in terms of hardware utilization compared to traditional methods. The design has been implemented on a range of FPGAs to compare the performance. The maximum frequency achieved is 114.27 MHz on XC5VLX330 FPGA and the maximum throughput, 1828.32 Mbit/s and minimum slice delay product, 9.18. The design is also implemented using synopsys DC synthesis in both 65 nm and 180 nm technology libraries. The advantages of multiplier-less architectures are reduced hardware and improved latency. The multiplier-less architectures for the implementation of radix-2^2 folded pipelined complex FFT core are based on NEDA. The number of points considered in the work is sixteen and the folding is done by a factor of four. The proposed designs are implemented on Xilinx XC5VSX240T FPGA. Proposed designs based on NEDA have reduced area over 83%. The observed slice-delay product for NEDA based designs are 2.196 and 5.735