63 research outputs found
Recommended from our members
Design techniques for clocking high performance signaling systems
Scaling of CMOS technology has progressed relentlessly for the past several
decades. In order for this unprecedented scaling to benefit the performance of
large digital systems, the communication bandwidth between integrated circuits
(ICs) must scale accordingly. However, interconnect technology does not scale as
aggressively, making communication between chips the major bottleneck in overall
system performance. In addition, supply voltage scaling, increasing device leakage,
and increased noise make existing signaling circuits inefficient and difficult to scale.
In this thesis, both analog and digital enhancement techniques to mitigate
scaling related issues and improve the performance of building blocks used in high-
speed signaling systems are discussed. A digital-to-phase converter (DPC) with a
resolution better than 100 femto-second resolution, a hybrid analog/digital clock
and data recovery (CDR) architecture that improves the tracking range of tra-
ditional CDRs by an order of magnitude, and a digital CDR architecture that
obviates the need for the charge pump and the large area occupying loop filter,
while achieving error-free operation are presented. Measured results obtained from
the prototype chips are presented to illustrate the proposed design techniques.Keywords: CDR, PL
A Modulo-Based Architecture for Analog-to-Digital Conversion
Systems that capture and process analog signals must first acquire them
through an analog-to-digital converter. While subsequent digital processing can
remove statistical correlations present in the acquired data, the dynamic range
of the converter is typically scaled to match that of the input analog signal.
The present paper develops an approach for analog-to-digital conversion that
aims at minimizing the number of bits per sample at the output of the
converter. This is attained by reducing the dynamic range of the analog signal
by performing a modulo operation on its amplitude, and then quantizing the
result. While the converter itself is universal and agnostic of the statistics
of the signal, the decoder operation on the output of the quantizer can exploit
the statistical structure in order to unwrap the modulo folding. The
performance of this method is shown to approach information theoretical limits,
as captured by the rate-distortion function, in various settings. An
architecture for modulo analog-to-digital conversion via ring oscillators is
suggested, and its merits are numerically demonstrated
Recommended from our members
A Multiplexer-Based Digital Passive Linear Counter (PLINCO)
A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n² for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded PLINCO also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.Keywords: digital circuits, thermometer code, low power, ones adderKeywords: digital circuits, thermometer code, low power, ones adde
- …