A route towards the fabrication of 2D heterostructures using atomic layer etching combined with selective conversion

Heterostructures of low-dimensional semiconducting materials, such as transition metal dichalcogenides (MX2), are promising building blocks for future electronic and optoelectronic devices. The patterning of one MX2 material on top of another one is challenging due to their structural similarity. This prevents an intrinsic etch stop when conventional anisotropic dry etching processes are used. An alternative approach consist in a two-step process, where a sacrificial silicon layer is pre-patterned with a low damage plasma process, stopping on the underlying MoS2 film. The pre-patterned layer is used as sacrificial template for the formation of the top WS2 film. This study describes the optimization of a cyclic Ar/Cl2 atomic layer etch process applied to etch silicon on top of MoS2, with minimal damage, followed by a selective conversion of the patterned Si into WS2. The impact of the Si atomic layer etch towards the MoS2 is evaluated: in the ion energy range used for this study, MoS2 removal occurs in the over-etch step over 1–2 layers, leading to the appearance of MoOx but without significant lattice distortions to the remaining layers. The combination of Si atomic layer etch, on top of MoS2, and subsequent Si-to-WS2 selective conversion, allows to create a WS2/MoS2 heterostructure, with clear Raman signals and horizontal lattice alignment. These results demonstrate a scalable, transfer free method to achieve horizontally individually patterned heterostacks and open the route towards wafer-level processing of 2D materials

Low damage cryogenic etching of low-K materials for advanced interconnects

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Preface to the Focus Issue on Atomic Layer Etch and Clean

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Improved Plasma Resistance for Porous Low-k Dielectrics by Pore Stuffing Approach

© 2014 The Electrochemical Society. The pore stuffing method is studied with the objective of improving the plasma induced damage for porous organo-silicate glass low-k dielectrics. Experiments on blanket films show that, pore stuffing reduces the low-k degradation compared to non-protected porous films during plasma etch. The post etch surface roughness is also improved. The protectionmechanism is attributed to reduced radical penetration, mainly fluorine and oxygen. The resistance against vacuum UV degradation is also improved by pore stuffing, since polymers used as filling agents have a higher VUV absorption coefficient than Si-O based dielectric network. The protection effect against fluorocarbon-based gas discharges is extensively studied with both blanket and patterned samples. For patterning of porous, non-stuffed low-k films, the addition of polymerizing gas reduces surface plasma damage but this polymerizing protection effect doesn't work well on trench sidewalls. Pore stuffing enables an efficient sidewall protection even with oxidizing gas discharges.status: publishe

Damage free integration of ultralow-k dielectrics by template replacement approach

© 2015 AIP Publishing LLC. Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constant of the gap-fill low-k is investigated on a 45 nm 1/2 pitch Meander-Fork structure, leading to keffbelow 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials.status: publishe

Alternative integration of ultra low-k dielectrics by template replacement approach

© 2015 IEEE. Replacement of sacrificial template by ultralow-k dielectric was studied as an alternative integration approach for Cu/low-k interconnect. Metallization structure was first formed by patterning a template material. After template removal, a spin-on porous low-k was deposited on the metal lines. Then, planarization of the excess low-k was performed by CMP. The proposed approach does solve the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous structures.status: publishe

Defect-induced bandgap narrowing in low-k dielectrics

© 2015 AIP Publishing LLC. In this work, core-level X-ray photoelectron spectroscopy was utilized to determine the surface bandgap for various porous and non-porous low-k a-SiCOH dielectrics before and after ion sputtering. By examining the onset of inelastic energy loss in O 1s core-level spectra, the gap narrowing was universally found in Ar+ion sputtered low-k dielectrics. The reduction of the bandgap ranges from 1.3 to 2.2eV depending on the film composition. We show that the bandgap narrowing in these low-k dielectrics is caused by development of the valence-band tail as evidenced by the presence of additional electronic states above the valence-band maximum. Electron-spin-resonance measurements were made on a-SiCOH films to gain atomic insight into the nature of the sputtering-induced defects and reveal formation of carbon-related defects as the most probable origin of the gap states.status: publishe

Ar and H2 plasma and neutral/ion beam treatment of EUV resist

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