Evolutionary Computing for Operating Point Analysis of Nonlinear Circuits

The DC operating point of an electronic circuit is conventionally found using the Newton-Raphson method. This method is not globally convergent and can only find one solution of the circuit at a time. In this paper, evolutionary computing methods, including Genetic Algorithms, Evolutionary Programming, Evolutionary Strategies and Differential Evolution are explored as possible alternatives to Newton-Raphson. These techniques have been implemented in a trial simulator. Results are presented showing that Evolutionary Computing methods are globally convergent and can find multiple solutions to circuits. The CPU time for these new methods is poor compared with Newton-Raphson, but better implementations and the use of hybrid methods suggest that further work in this area would prove fruitful

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Simultaneous Optimisation of Dynamic Power, Area and Delay in Behavioural Synthesis

Concern over power dissipation coupled with the continuing rise in system size and complexity means that there is a growing need for high-level design tools capable of automatically optimising systems to take into account power dissipation, in addition to the more conventional metrics of area, delay and testability. Current methods for reducing power consumption tend to be ad-hoc: for example, slowing down, or turning off idle parts of the system, or a controlled reduction in power supply. The behavioural synthesis system described in this paper features an integrated incremental power estimation capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate circuit-level cell models (generated, again automatically, via Spice simulation); and a comprehensive system power model. This data, along with similar estimators for area and delay, guides the optimisation of a design towards independent, user-specified objectives for final area, delay, clock speed, and energy consumption. In addition, a range of power reducing features are included encompassing: supply voltage scaling, clock gating, input latching, input gating, low-power cells, and pipelined and multicycle units. These are automatically exploited during optimisation as part of the area/delay/power dissipation trade-off process. The resulting system is capable of reducing the estimated energy consumption of several benchmark designs by factors of between 3.5 and 7.0 times. Furthermore, the design exploration capability enables a range of alternative structural implementations to be generated from a single behavioural description, with differing area/delay/power trade-offs

Meeting the design challenges of nano-CMOS electronics: an introduction to an upcoming EPSRC pilot project

The years of ‘happy scaling’ are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems. This paper provides an introduction to these challenges and gives an overview of the Grid infrastructure that will be developed as part of a recently funded EPSRC pilot project to address them, and we hope, which will revolutionise the electronics design industry

Étude des marqueurs génétiques sanguins dans deux races de poneys de pologne

International audienc

Denudation and geomorphic change in the Anthropocene; a global overview

The effects of human activity on geomorphic processes, particularly those related to denudation/sedimentation, are investigated by reviewing case studies and global assessments covering the past few centuries. Evidence we have assembled from different parts of the world, as well as from the literature, show that certain geomorphic processes are experiencing an acceleration, especially since the mid-twentieth century. This suggests that a global geomorphic change is taking place, largely caused by anthropogenic landscape changes