Developing a method for elaboration the scenarios related with sustainable products lifecycle

This article aims at presenting our objective that is to use DfD rules earlier during the design process. Indeed, during the conceptual design phase, designers don't have simple qualitative tools or methods to evaluate their products. There are guidelines that are very useful in a first approach to give some objectives, but there is no quantitative indicators associated to these rules to consider the disassembly aspects when the first choices are realised for the product. So we will present that to use DfD rules during the conceptual design phase, we first have: ?to identify which kind of rules can be applied when designers only have a functional representation of their product. ?to create the necessary indicators to evaluate these rules depending on designers choices. We think that this approach is usable for many DfX rules either if we only consider in this paper DfD rules.Comment: 10 Pages; 1st International Engineering Sciences Conference 2008, Aleppo : Syrian Arab Republic (2008

An improved instruction-level power model for ARM11 microprocessor

The power and energy consumed by a chip has become the primary design constraint for embedded systems, which has led to a lot of work in hardware design techniques such as clock gating and power gating. The software can also affect the power usage of a chip, hence good software design can be used to reduce the power further. In this paper we present an instruction-level power model based on an ARM1176JZF-S processor to predict the power of software applications. Our model takes substantially less input data than existing high accuracy models and does not need to consider each instruction individually. We show that the power is related to both the distribution of instruction types and the operations per clock cycle (OPC) of the program. Our model does not need to consider the effect of two adjacent instructions, which saves a lot of calculation and measurements. Pipeline stall effects are also considered by OPC instead of cache miss, because there are a lot of other reasons that can cause the pipeline to stall. The model shows good performance with a maximum estimation error of -8.28\% and an average absolute estimation error is 4.88\% over six benchmarks. Finally, we prove that energy per operation (EPO) decreases with increasing operations per clock cycle, and we confirm the relationship empirically

Modelling Smart Card Security Protocols in SystemC TLM

Smart cards are an example of advanced chip technology. They allow information transfer between the card holder and the system over secure networks, but they contain sensitive data related to both the card holder and the system, that has to be kept private and confidential. The objective of this work is to create an executable model of a smart card system, including the security protocols and transactions, and to examine the strengths and determine the weaknesses by running tests on the model. The security objectives have to be considered during the early stages of systems development and design, an executable model will give the designer the advantage of exploring the vulnerabilities early, and therefore enhancing the system security. The Unified Modeling Language (UML) 2.0 is used to model the smart card security protocol. The executable model is programmed in SystemC with the Transaction Level Modeling (TLM) extensions. The final model was used to examine the effectiveness of a number of authentication mechanisms with different probabilities of failure. In addition, a number of probable attacks on the current security protocol were modeled to examine the vulnerabilities. The executable model shows that the smart card system security protocols and transactions need further improvement to withstand different types of security attacks

Product ecodesign and materials: current status and future prospects

The aim of this paper is to discuss the current status of ecodesign in the industry and its future implications for materials. There is today more and more focus on the environmental impacts of products during their whole life cycle. In particular, ecodesign aims at integrating environmental aspects during the product's design process as any other criterion, in order to reduce the life cycle impacts. Although a lot of product environmental impact assessment and Design for Environment tools already exist, environmental aspects are unfortunately rarely routinely integrated into product development process in the industry. This is mainly due to the fact that current ecodesign tools are little adapted to designers' practices, requirements and competencies. After the sequential and DfX paradigms, design of products is today maturing into Integrated Design, where multiple points of views and expertise have to be considered at the same time to progressively define the product

Evolutionary Computing for Operating Point Analysis of Nonlinear Circuits

The DC operating point of an electronic circuit is conventionally found using the Newton-Raphson method. This method is not globally convergent and can only find one solution of the circuit at a time. In this paper, evolutionary computing methods, including Genetic Algorithms, Evolutionary Programming, Evolutionary Strategies and Differential Evolution are explored as possible alternatives to Newton-Raphson. These techniques have been implemented in a trial simulator. Results are presented showing that Evolutionary Computing methods are globally convergent and can find multiple solutions to circuits. The CPU time for these new methods is poor compared with Newton-Raphson, but better implementations and the use of hybrid methods suggest that further work in this area would prove fruitful

Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

Review of Horacio Spector, Autonomy and Rights: The Moral Foundations of Liberalism

Work reviewed: Autonomy and Rights: The Moral Foundations of Liberalism by Horacio Spector Horacio Spector, Autonomy and Rights: The Moral Foundations of Liberalism (Oxford: Oxford University Press, 1992) ISBN 978019953362

Price Gouging, Non-Worseness, and Distributive Justice

This paper develops my position on the ethics of price gouging in response to Jeremy Snyder\u27s article, What\u27s the Matter with Price Gouging. First, it explains how the nonworseness claim supports the moral permissibility of price gouging, even if it does not show that price gougers are morally virtuous agents. Second, it argues that questions about price gouging and distributive justice must be answered in light of the relevant possible institutional alternatives, and that Snyder\u27s proposed alternatives to price gouging fare worse on the dimension of justice than a system in which goods are allocated by a system of market prices

Testing of Level Shifters in Multiple Voltage Designs

The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage can be achieved in the PASSIVE mode. We consider resistive opens and shorts and show that, for testing purposes, consideration of purely digital fault effects is sufficient. Thus conventional digital DfT can be employed to test level shifters. In all cases, we conclude that using sets of single supply voltages for testing is sufficient