A low power and fast CMOS arithmetic logic unit

This thesis presents the design of a low power and fast Complimentary Metal-Oxide- Semiconductor (CMOS) Arithmetic Logic Unit (ALU). ALU is one of the most important parts of a digital computer which is designed to do the arithmetic and logic operations, including bit shifting operation that need to be done for almost any data that is being processed by the central processing unit (CPU). For most applications of all digital circuits, the two important attributes are maximizing speed and minimizing power consumption. The overall performance of the system will depend on the speed of the different modules used in the design. To achieve the desired outcome, the proposed ALU is designed using pass transistor logic (PTL) based multiplexers and 8 transistors (8T) full adder. Tanner EDA V13 with CMOS technology of 0.25μm is used to design and analyze the circuit. Less number of transistors used will result in small design space area thus reducing the power consumption. The result is being analyzed by different values of supply voltage applied to the circuit which ranging from 5V to 1V. The results obtained shows that the minimum power consumption is for Vdd equal to 1V with 0.533μW. The speed of the circuit is being measured through the propagation delay of the ALU. The result shows the propagation delay for 1V power supply is 3.65μs