19 research outputs found

    Packet clock recovery using a bismuth oxide fiber-based optical power limiter

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    Abstract: We demonstrate an optical clock recovery circuit that extracts the line rate component on a per packet basis from short data packets at 40 Gb/s. The circuit comprises a Fabry-Perot filter followed by a novel power limiting configuration, which in turn consists of a 5m highly nonlinear bismuth oxide fiber in cascade with an optical bandpass filter. Both experimental and simulation-based results are in close agreement and reveal that the proposed circuit acquires the timing information within only a small number of bits, yielding a packet clock for every respective data packet. Moreover, we investigate theoretically the scaling laws for the parameters of the circuit for operation beyond 40 Gb/s and present simulation results showing successful packet clock extraction for 160 Gb/s data packets. Finally, the circuit's potential for operation at 320 Gb/s is discussed, indicating that ultrafast packet clock recovery should be in principle feasible by exploiting the passive structure of the device and the fsec-scale nonlinear response of the optical fiber

    2 × 2 exchange/bypass switch using 0.8 m of highly nonlinear bismuth oxide fiber

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    Optically controlled 2x2 exchange/bypass switch with 0.8 m of Bismuth Oxide nonlinear fibre

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    A 40 Gbps all-optical label/payload separation circuit Using hybrid integrated MZI switches

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    All-optical label/payload separation at 40 Gb/s

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    Single chip quad MZI array in a 40 Gb/s AOLS front-end

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