Leveraging RRAM to Design Efficient Digital Circuits and Systems for Beyond Von Neumann in-Memory Computing

Due to the physical separation of their processing elements and storage units, contemporary digital computers are confronted with the thorny memory-wall problem. The strategy of in-memory computing has been considered as a promising solution to overcome the von Neumann bottleneck and design high-performance, energy-efficient computing systems. Moreover, in the post Moore era, post-CMOS technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. Motivated by these perspectives from system level to device level, this thesis proposes two effective processing-in-memory schemes to construct the non-von Neumann systems based on nonvolatile resistive random-access memory (RRAM). In the first scheme, we present functionally complete stateful logic gates based on a CMOS-compatible 2-transistor-2-RRAM (2T2R) structure. In this structure, the programmable logic functionality is determined by the amplitude of operation voltages, rather than its circuit topology. A reconfigurable 3T2R chain with programmable interconnects is used to implement complex combinational logic circuits. The design has a highly regular and symmetric circuit structure, making it easy for design, integration, and fabrication, while the operations are flexible yet clean. Easily integrated as 3-dimensional (3-D) stacked arrays, two proposed memory architectures not only serve as regular 3-D memory arrays but also perform in-memory-computing within the same layer and between the stacked layers. The second scheme leverages hybrid logic in the same hardware to design efficient digital circuits and systems with low computational complexity. Multiple-bit ripple-carry adder (RCA), pipelined RCA, and prefix tree adder are shown as example circuits, using the same regular chain structure, to validate the design efficiency. The design principles, computational complexity, and performance are discussed and compared to the CMOS technology and other state-of-the-art post-CMOS implementations. The overall evaluation shows superior performance in speed and area. The result of the study could build a technology cell library that can be potentially used as input to a technology-mapping algorithm. The proposed hybrid-logic methodology presents prospect of hardware acceleration and future beyond-von Neumann in-memory computing architectures

Electronic Structure and Optical Properties of the Co-doped Anatase TiO2_{2} Studied from First Principles

The Co-doped anatase TiO$_{2}$, a recently discovered room-temperature ferromagnetic insulator, has been studied by the first-principles calculations in the pseudo-potential plane-wave formalism within the local-spin-density approximation (LSDA), supplemented by the full-potential linear augmented plane wave (FP-LAPW) method. Emphasis is placed on the dependence of its electronic structures and linear optical properties on the Co-doping concentration and oxygen vacancy in the system in order to pursue the origin of its ferromagnetism. In the case of substitutional doping of Co for Ti, our calculated results are well consistent with the experimental data, showing that Co is in its low spin state. Also, it is shown that the oxygen vacancy enhances the ferromagnetism and has larger effect on both the electronic structure and optical properties than the Co-doping concentration only.Comment: 12 pages, 4 figure

A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters

Real time electricity monitoring is critical to enable intelligent and customized energy management for users in residential, educational, and commercial buildings. This paper presents the design, integration, and testing of a simple, self-contained, low-power, non-invasive system at low cost applicable for such purpose. The system is powered by piezoelectric energy harvesters (EHs) based on PZT and includes a microcontroller unit (MCU) and a central hub. Real-time information regarding the electricity consumption is measured and communicated by the system, which ultimately offers a dependable and promising solution as a wireless sensor node. The dynamic power management ensures the system to work with different types of PZT EHs at a wide range of input power. Thus, the system is robust against fluctuation of the current in the electricity grid and requires minimum adjustment if EH unit requires exchange or upgrade. Experimental results demonstrate that this unit is in a position to read and transmit 60 Hz alternating current (AC) sensor signals with a high accuracy no less than 91.4%. The system is able to achieve an operation duty cycle from <1 min up to 18 min when the current in an electric wire varies from 7.6 A to 30 A, depending on the characteristics of different EHs and intensity of current being monitored

The electronic structure of LaCo

The electronic structure of the recently discovered LaCo2B2 was studied from first-principles calculations. Our results indicate that the hybridization between Co-3d and B-2p is much stronger than that between Fe-3d and As-4p in LaOFeAs and BaFe2As2, which removes the magnetic ordering of Co ions. Therefore, the ground state of LaCo2B2 is nonmagnetic. At the Fermi level, the density of state of La-5d is very high and here are four bands cutting across the Fermi level, which are mostly derived from dz2−3r2 and dyz/zx orbitals. Such results are different with both LaOFeAs and BaFe2As2. The substitution of La by Y atoms would not change the ground state, while substitution of La with Sc atoms might induce a magnetic moment on the Co atom. Comparing with LuNi2B2C2, we classify LaCo2B2 as a BCS superconductor

Scalable 2T2R Logic Computation Structure: Design From Digital Logic Circuits to 3-D Stacked Memory Arrays

In the post Moore era, post-complementary metal–oxide–semiconductor (CMOS) technologies have received intense interests for possible future digital logic applications beyond the CMOS scaling limits. In the meantime, from the system perspective, non-von Neumann architectures, such as processing-in-memory (PIM), are extensively explored to overcome the bottleneck of modern computers, known as the memory wall, for high-performance energy-efficient integrated circuits. In this article, we propose functionally complete nonvolatile logic gates based on a two-transistor-two-resistive random access memory (RRAM) (2T2R) unit structure, which is then used to form a reconfigurable three-transistor-two-RRAM (3T2R) chain with programmable interconnects for complex combinational logic circuits, and a dense 3-D stacked memory array architecture. The design has a highly regular and symmetric structure, while operations are flexible yet simple, without the need of complicated peripheral circuitry or a third resistive state. Implementations of XNOR gate and full adder using 3T2R chain without extra routing/control gates or resistors are shown as demonstration examples of arithmetic unit design. The proposed computing scheme is intrinsic, efficient with superior performance in speed and area. Easily integrated as 3-D stacked array, the proposed memory architecture not only serves as regular 3-D memory array but also performs logic computation within the same layer and between the stacked layers. Concurrent computations under multiple computation modes for flexible operations in the memory are presented. Bias schemes for selected/half-selected/unselected cells are also explained and verified