A Message-Passing, Thread-Migrating Operating System for a Non-Cache-Coherent Many-Core Architecture

The difference between emerging many-core architectures and their multi-core predecessors goes beyond just the number of cores incorporated on a chip. Current technologies for maintaining cache coherency are not scalable beyond a few dozen cores, and a lack of coherency presents a new paradigm for software developers to work with. While shared memory multithreading has been a viable and popular programming technique for multi-cores, the distributed nature of many-cores is more amenable to a model of share-nothing, message-passing threads. This model places different demands on a many-core operating system, and this thesis aims to understand and accommodate those demands. We introduce Xipx, a port of the lightweight Embedded Xinu operating system to the many-core Intel Single-chip Cloud Computer (SCC). The SCC is a 48-core x86 architecture that lacks cache coherency. It features a fast mesh network-on-chip (NoC) and on-die message passing buffers to facilitate message-passing communications between cores. Running as a separate instance per core, Xipx takes advantage of this hardware in its implementation of a message-passing device. The device multiplexes the message passing hardware, thereby allowing multiple concurrent threads to share the hardware without interfering with each other. Xipx also features a limited framework for transparent thread migration. This achievement required fundamental modifications to the kernel, including incorporation of a new type of thread. Additionally, a minimalistic framework for bare-metal development on the SCC has been produced as a pragmatic offshoot of the work on Xipx. This thesis discusses the design and implementation of the many-core extensions described above. While Xipx serves as a foundation for continued research on many-core operating systems, test results show good performance from both message passing and thread migration suggesting that, as it stands, Xipx is an effective platform for exploration of many-core development at the application level as well

6.4 GHz Acoustic Sensor for In-situ Monitoring of AFM Tip Wear

This paper demonstrates an acoustic sensor that can resolve atomic force microscopy (AFM) tip blunting with a frequency sensitivity of 0.007%. The AFM tip is fabricated on a thin film piezoelectric aluminum nitride (AlN) membrane that is excited as a film bulk acoustic resonator (FBAR). We demonstrate that cutting 0.98 μm off of the tip apex results in a resonance frequency change of 0.4MHz at 6.387GHz. This work demonstrates the potential for in-situ monitoring of AFM tip wear

A Down-to-Earth Educational Operating System for Up-in-the-Cloud Many-Core Architectures

We present Xipx, the first port of a major educational operating system to a processor in the emerging class of many-core architectures. Through extensions to the proven Embedded Xinu operating system, Xipx gives students hands-on experience with system programming in a distributed message-passing environment. We expose the software primitives needed to maintain coherency between many cores in a system lacking specialized caching hardware. Our proposed series of laboratory assignments adds parallel thread execution and inter-core message passing communication to a well-established OS curriculum

Integrated Freestanding Single-Crystal Silicon Nanowires: Conductivity and Surface Treatment

Integrated freestanding single-crystal silicon nanowires with typical dimension of 100 nm × 100 nm × 5 µm are fabricated by conventional 1:1 optical lithography and wet chemical silicon etching. The fabrication procedure can lead to wafer-scale integration of silicon nanowires in arrays. The measured electrical transport characteristics of the silicon nanowires covered with/without SiO2 support a model of Fermi level pinning near the conduction band. The I–V curves of the nanowires reveal a current carrier polarity reversal depending on Si–SiO2 and Si–H bonds on the nanowire surface

Nano-electromechanical Zero-dimensional Freestanding Nanogap Actuator

Micromachined free standing nanogap with metal electrodes is presented. The gap size is as small as 17 nm, and can be reduced further with electrostatic or piezoelectric actuation. The nanoscale gap is fabricated by industrial standard optical lithography and anisotropic wet chemical Si etching. Electron transport between the metal electrodes with optical stimulus enhancing photon-electron coupling (plasmon) is presented

BareMichael: A minimalistic Bare-metal Framework for the Intel SCC

The many-core Intel SCC processor is one of a class of emerging, highly parallel computer architectures. Intel provides a modern Linux kernel which, running on the SCC as a separate instance per core, is able to load and launch user applications. However, there is a lack of open-source tools to facilitate development of “bare-metal” SCC applications – applications that are run directly on the chip without the support, overhead, or restrictiveness of an underlying operating system. To help fill this void, we present BareMichael, a minimalistic framework for compiling, loading, and launching mixed C and assembly code on the bare-metal Intel SCC. The framework also includes MikeTerm, a one-way pseudo-terminal for displaying output from an application as it executes on the chip. We share our solution in the hope that it will lower the barrier for others to begin development in a bare-metal environment on the SCC. Furthermore, we demonstrate the utility of BareMichael through two applications: supporting the use of the RCCE messagepassing library, and serving as the foundation for a port of the Embedded Xinu operating system