Power consumption reduction techniques for H.264 video compression hardware

Video compression systems are used in many commercial products such as digital camcorders, cellular phones and video teleconferencing systems. H.264 / MPEG4 Part 10, the recently developed international standard for video compression, offers significantly better compression efficiency than previous video compression standards. However, this compression efficiency comes with an increase in encoding complexity and therefore in power consumption. Since portable devices operate with battery, it is important to reduce power consumption so that battery life can be increased. In addition, consuming excessive power degrades the performance of integrated circuits, increases packaging and cooling costs, reduces reliability and may cause device failures. In this thesis, we propose novel computational complexity and power reduction techniques for intra prediction, deblocking filter (DBF), and intra mode decision modules of an H.264 video encoder hardware, and intra prediction with template matching (TM) hardware. We quantified the computation reductions achieved by these techniques using H.264 Joint Model reference software encoder. We designed efficient hardware architectures for these video compression algorithms and implemented them in Verilog HDL. We mapped these hardware implementations to Xilinx Virtex FPGAs and estimated their power consumptions using Xilinx XPower Analyzer tool. We integrated the proposed techniques to these hardware implementations and quantified their impact on the power consumptions of these hardware implementations on Xilinx Virtex FPGAs. The proposed techniques significantly reduced the power consumptions of these FPGA implementations in some cases with no PSNR loss and in some cases with very small PSNR loss

Energy reduction techniques for H.264 deblocking filter hardware

In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 Deblocking Filter (DBF) algorithm, and therefore reducing the energy consumption of H.264 DBF hardware. These techniques avoid unnecessary calculations in H.264 DBF algorithm by exploiting the equality and similarity of the pixels used in DBF equations. The proposed techniques reduce the amount of addition and shift operations performed by H.264 DBF algorithm up to 52% and 67% respectively with a small comparison overhead. The pixel equality based technique does not affect PSNR. The pixel similarity based technique does not affect the PSNR for some video frames, but it decreases the PSNR slightly for some video frames. We also implemented an efficient H.264 DBF hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the energy consumption of this H.264 DBF hardware up to 35% and 39%, respectively. Therefore, they can be used in portable consumer electronics products that require real-time video compression

A novel energy reduction technique for H.264 intra mode decision

In this paper, we propose a novel energy reduction technique for H.264 intra mode decision. The proposed technique reduces the number of additions performed by Sum of Absolute Transformed Difference based 4×4, 16×16 and 8×8 intra mode decision algorithms used in H.264 joint model reference software encoder by 46%, 43% and 42% respectively for a CIF size frame without any PSNR loss. We also implemented an efficient H.264 16×16 intra mode decision hardware including the proposed technique using Verilog HDL. The proposed technique reduced the energy consumption of this H.264 16×16 intra mode decision hardware up to 59.6%

A computation and energy reduction technique for H.264 deblocking filter hardware (H.264 blok giderici filtre donanımının işlem miktarını ve enerji kullanımını azaltan teknik)

In this paper, we propose pixel equality based technique to reduce the amount of computations performed by H.264 Deblocking Filter (DBF) algorithm and therefore reduce the energy consumption of H.264 DBF hardware. This technique exploits pixel equality in a video frame by performing a small number of comparisons among edge pixels used in DBF equations before the filtering. If the input pixels are equal, DBF equations simplify significantly. The proposed technique reduces the amount of addition and shift operations performed by H.264 DBF algorithm up to 43% and 55% respectively with a small comparison overhead. The pixel equality based technique does not affect PSNR. We also implemented an efficient H.264 DBF hardware including the proposed technique using Verilog HDL. The proposed pixel equality based technique reduced the energy consumption of this hardware up to 35%

A Novel computational complexity and power reduction technique for H.264 intra prediction

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a novel technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly without any PSNR and bitrate loss. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are equal, the prediction equations of H.264 intra prediction modes simplify significantly for this block. By exploiting the equality of the neighboring pixels, the proposed technique reduces the amount of computations performed by 4x4 luminance, 16x16 luminance, and 8x8 chrominance prediction modes up to 60%, 28%, and 68% respectively with a small comparison overhead. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. We quantified the impact of the proposed technique on the power consumption of this hardware on a Xilinx Virtex II FPGA using Xilinx XPower, and it reduced the power consumption of this hardware up to 18.6%

A high performance deblocking filter hardware for high efficiency video coding

The recently developed High Efficiency Video Coding (HEVC) international video compression standard uses adaptive deblocking filter for reducing blocking artifacts. Deblocking filters increase both subjective and objective quality. But, they have high computational complexity. Therefore, in this paper, the first HEVC deblocking filter hardware in the literature is proposed. Two parallel datapaths are used in the proposed hardware in order to increase its performance. The proposed hardware is implemented in Verilog HDL. The Verilog RTL code is verified to work correctly on an FPGA board. The proposed HEVC deblocking filter hardware can code 30 full HD (1920x1080) video frames per second. Therefore, it can be used in consumer electronics products that require a real-time HEVC encoder or decoder.(1

A high performance and low energy intra prediction hardware for high efficiency video coding

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4×4 and 8×8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4×4 and 8×8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA