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1 research outputs found
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme
Author
Go MATSUKAWA
Hiroshi KAWAGUCHI
+7Â more
Masafumi SHIMOZAWA
Masahiko YOSHIMOTO
Shigeru OHO
Shuhei YOSHIDA
Yasuo SUGURE
Yohei NAKATA
Yuta KIMI
Publication venue
'Institute of Electronics, Information and Communications Engineers (IEICE)'
Publication date
01/01/2015
Field of study
No full text
Crossref
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