CORE
🇺🇦Â
 make metadata, not war
Services
Services overview
Explore all CORE services
Access to raw data
API
Dataset
FastSync
Content discovery
Recommender
Discovery
OAI identifiers
OAI Resolver
Managing content
Dashboard
Bespoke contracts
Consultancy services
Support us
Support us
Membership
Sponsorship
Community governance
Advisory Board
Board of supporters
Research network
About
About us
Our mission
Team
Blog
FAQs
Contact us
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme
Authors
Go MATSUKAWA
Hiroshi KAWAGUCHI
+7Â more
Masafumi SHIMOZAWA
Masahiko YOSHIMOTO
Shigeru OHO
Shuhei YOSHIDA
Yasuo SUGURE
Yohei NAKATA
Yuta KIMI
Publication date
1 January 2015
Publisher
'Institute of Electronics, Information and Communications Engineers (IEICE)'
Doi
Cite
Abstract
Abstract is not available.
Similar works
Full text
Available Versions
Crossref
See this paper in CORE
Go to the repository landing page
Download from data provider
info:doi/10.1587%2Ftransele.e9...
Last time updated on 11/11/2020