Hardware Modelling of a PLC Multipath Channel Transfer Function

PLC channel transfer functions are critical in developing channel emulators. Emulators are used to test PLC transceivers that would have been otherwise tested on a live network which is not only hazardous but also is not repetitive since the PLC network's characteristics vary with time and frequency. The PLC channel transfer function that is considered here is the multipath channel model of Zimmermann and Dostert. Zimmermann's multipath channel transfer function includes not only the attenuation experienced by the signal, but also the phase change due to the multipath. The inclusion of the phase in the transfer function requires the processing of imaginary numbers in the FPGA. Euler's theorem is used to convert from the polar form to the rectangular form of the transfer function. This paper focuses on the hardware modelling of the rectangular form using Hardware Description Language. The real and imaginary components of the rectangular form are modelled as two circuit models. The designed channel transfer function module uses fixed point (FP) format. The HDL model was successfully synthesized to a hardware equivalence using the XILINX ISE tool. XILINX core generator was used for the CORDIC module that computes the sine, cosine, hyperbolic sine and hyperbolic cosine functions. Simulation result of the hardware model revealed an accuracy of up to at least 3 decimal places when compared to the theoretical results using Excel or Matlab

Development of a Wideband PLC Channel Emulator with Random Noise Scenarios

Channel emulators are an integral part of the test equipment that offers a more practical approach to testing new communication devices. It is imperative though to develop the emulator such that it best represents the channel. For PLC channel emulator, the channel representation can be either topdown or bottom-up. In this paper, the top-down characterisation and reference channels are used. In this approach, statistical measurements of the characteristics of the power line were conducted, and the closest mathematical representation is presented. The emulator operates in the frequency domain utilising 4096 transform points for the FFT process and 14 fractional bits for fixed point presentation. This number of bits allowed the emulator to sufficiently generate an average of 0.4% error between the software simulation results and the hardware test results. The input signal is converted to an LVDS signal by the FMC151 which serves as the AFE of the emulator. Two linear regulators block are used to convert both the negative and positive values of the input signal. The random generation of noise reduced the taxing efforts of adding different combinations of noise thus providing ease in focusing on the analysis of the resulting waveform

Pneumococcal conjugate vaccine implementation in middle-income countries

Since 2000, the widespread adoption of pneumococcal conjugate vaccines (PCVs) has had a major impact in the prevention of pneumonia. Limited access to international financial support means some middle-income countries (MICs) are trailing in the widespread use of PCVs. We review the status of PCV implementation, and discuss any needs and gaps related to low levels of PCV implementation in MICs, with analysis of possible solutions to strengthen the PCV implementation process in MICs

Programmable cyclic redundancy check encoder

Known for its high efficiency in detecting error on transmitted data, CRC (Cyclic Redundancy Check) comes in 4 common types, namely: CRC-12, CRC-16, CRC-CCITT and CRC-32. This project presents the features of the 4 CRC\u27s and their applications in the field of data communication. A module combining the 4 CRSs into one programmable circuit shall be designed. This will then be implemented as one chip using VLSI technology with the help of CAD (Computer Aided Design) tools. Hardware implementation and software simulation shall be provided to verify the validity of the design

Hardware modeling development of a convolutional neural network with K-means-clustered weights in rapid prototyping systems: Advances and limitations

Neural networks and clustering are two of the many machine learning algorithms used for artificial intelligence. The conventional neural network is made up of numerous fully connected layers of neutrons. On the other hand, Convolutional Neural Networks (CNN) have become a better alternative to the conventional neural network due its ability to provide better guarantee for training success. In designing a hardware model for the CNN, emphasis is not only focused hardware requirement for the size and number of processing layers but also to the those needed by the weight values. In this research, a hardware model design for a CNN architecture is presented. The hardware model is capable of training by itself without the aid of any external or co processor. A hardware model design for the K-means clustering algorithm is also presented. The K-means clustering model is intended to compress the weights of the CNN in order to save hardware requirement for implementation. The CNN model and the K-means clustering model are then integrated to develop a CNN architecture that can perform weight compression by itself after training. The two hardware models are synthesized and implemented using a XILINX Virtex 5 library. Small scale CNN for pattern recognition shows the CNN can still recognize the input patterns at a compression rate of up to 80%. Another small scale CNN for selected digit image recognition shows 100% recognition of trained inputs up to 60% compression. The integration, when synthesized using the Virtex 5 library consumes 29,163 slice registers, 28,896 flip flops and 55,645 look up tables

Design and characterization of fully integrated low frequency, low voltage 0.25μm CMOS clock generator circuit

When designing an integrated circuit, simulation should normally pass through 5 corner libraries. The ideal case is to have the simulation results showing the same performance for all the corner libraries. However, owing to the difference in specifications among libraries, there can be significant variations of one result over another per library. In this paper, a fully integrated CMOS RC Clock circuit topology design is presented. The circuit was designed to have minimal sensitivity to process corner library variations. The design can operate at a low voltage of 1.5V using the 0.25um library. Simulation shows the clock output frequency remains stable at 50 kHz for all process corner libraries with a maximum deviation of only 6%. An added feature of the circuit is the variation of the clock\u27s duty cycle. The entire design is fitted in an area of 1.11um2. © 2014 IEEE

Design, development and implementation of a fuzzy logic controller for DC-DC buck and boost converter in an FPGA

A fuzzy logic controller for DC-DC Buck and Boost converters is designed and presented in this paper. The mathematical model of buck and boost converter and fuzzy logic controller are first derived then converted to a hardware model using VHSIC Hardware Description Language. The hardware model was subsequently synthesized and implemented in a Field programmable Gate Array (FPGA) chip. In order to confirm that the mathematical model gives stable output frequency, simulation on MATLAB is made. To verify the effectiveness of the simulation model, an experimental set up is developed. An FPGA-based fuzzy logic controller was implemented and interfaced to a DC-DC converter module. The system was tested using white LEDs as loads. Simulation and experimental results show that the DC-DC converter is able to maintain the output based on the value set inside the controller module. © 2013 IEEE

Design and development of audit central data bank at Ibiden Philippines, Inc. (IPI)

In most of the companies in the Philippines, audit findings and results are monitored manually. This method offers inaccessible and unreliable data that invokes downtime in audit issuance, audit response, audit verification and implementation, and audit closure as well. It showcased a process system of less priority and consideration on Productivity, Quality, Cost, Delivery and Morale. The proponent thought of a way to develop a central repository or data bank of audit findings to easily retrieve the audits conducted by IQA, PQA, IEA, TPM and other auditing bodies and to provide robust monitoring of Audit Issuance, Audit Response, Audit Verification (Verification of Implementation) and Audit Closure (Verification of Effectiveness). Audit Central Data Bank in Ibiden Philippines, Inc. is a PC-based centralized macro program. It is software that consolidates all audit results of each auditing body (IQA, PQA, IEA, TPM, YIP and External Supplier). It performs common tasks and functions understood and applied by entire IPI community. © 2012 IEEE