Vertical Transistors: a Slippery Path towards the Ultimate CMOS Scaling

The semiconductor industry has largely relied on Moore’s law, based on the observation that every new generation of transistors has been better than the previous one in Power, Performance, Area and Cost (PPAC) metrics simultaneously. However, this trend is under a pressure now. The main issue is related to the enormous complexity of both technology and design, which drastically raises not only the manufacturing, but also the R&D costs. Therefore, in order to minimize risks and maximize benefits of a new technology, it is being co-optimized hand in hand with a design relying on this technology. The scaling of lateral transistors is going to reach its limit soon because it mainly relies on the scaling of contacted gate pitch (CGP), which, in turn, forces the scaling of gate length, S/D spacers and contacts. Reduction of any of these dimensions is undesirable as it leads to poorer electrostatic control, increased parasitic capacitance and increased access resistance, respectively. There are lateral devices, like nanowire-based FETs, which may postpone the problem of CGP budgeting but they cannot solve it. The focus of this PhD work is on the vertical devices. These devices are less constrained on gate length and spacer thickness as they are oriented vertically and thus should demonstrate better scalability than lateral transistors. We quantify the advantages of the vertical devices in terms of PPA metrics through a holistic benchmark by combining the design techniques and technology limitations which are likely to be in place at the 5nm technology. In order to do this, we perform the layouts analysis, model and evaluate RC parasitics, calibrate compact models to TCAD and experimental data. Afterwards, we run simulations on a ring oscillator level to extract the PPA metrics. We have not limited ourselves to the conventional MOSFETs only, but we also benchmark vertical III-V heterojunction Tunnel FETs in order to get a better understanding under which conditions the vertical architecture is the most advantageous. This allows us to shed light on the ultimate CMOS scaling and to understand whether the introduction of vertical transistors can enable the next technological nodes.nrpages: 143status: publishe

Process-Induced Power-Performance Variability in Sub-5nm III-V Tunnel FETs

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve <18x speed loss and <3x energy penalty for (0.1-1) ns gate delay with respect to the nominal corner.status: Published onlin

Trap-Aware Compact Modeling and Power-Performance Assessment of III-V Tunnel FET

We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ~5x iso-frequency energy penalty in the desired low-supply-voltage domain (≤0.50V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET.status: publishe

Trap-aware compact modeling and power-performance assessment of III-V tunnel FET

We report, for the first time, on a SPICE simulation study of the circuit-level power-performance impact of device traps in a state-of-the-art III-V heterojunction tunnel FET (TFET). First, the individual parasitic effects of junction bulk traps and oxide interface traps are incorporated in a compact model and validated against measurement-calibrated TCAD data, where we propose an analytical formulation for trap-assisted tunneling at the heterojunction and account for the oxide interface charge with a look-up table. Then, the model is used in SPICE simulations on a ring oscillator test bench to predict the impact of traps on logic circuits. It is found that bulk and oxide traps in TFET together cause up to ∼5x iso-frequency energy penalty in the desired low-supply-voltage domain (0.50 V), of which oxide traps dominate at high switching activity while bulk and oxide traps contribute comparably when switching is less active. This study quantitatively suggests that trap reduction is the key to the enablement of the full benefit of TFET

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

status: publishe