5 research outputs found
Security Analysis of the Silver Bullet Technique for RowHammer Prevention
The purpose of this document is to study the security properties of the
Silver Bullet algorithm against worst-case RowHammer attacks. We mathematically
demonstrate that Silver Bullet, when properly configured and implemented in a
DRAM chip, can securely prevent RowHammer attacks. The demonstration focuses on
the most representative implementation of Silver Bullet, the patent claiming
many implementation possibilities not covered in this demonstration. Our study
concludes that Silver Bullet is a promising RowHammer prevention mechanism that
can be configured to operate securely against RowHammer attacks at various
efficiency-area tradeoff points, supporting relatively small hammer count
values (e.g., 1000) and Silver Bullet table sizes (e.g., 1.06KB).Comment: 40 page
Design of an fpga based co-processor for digital signal processing applications
Sayısal sinyal işlemede yaygın olarak büyük veri setleri üzerinde kullanılan fonksiyonların hızlandırılması için günümüzde çok çekirdekli işlemciler, grafik işlemciler, FPGA tabanlı sistemler ve ASIC tasarımlar kullanılarak paralel hesaplama ile sağlanır. Bu tez çalışması, ASELSAN - TOBB ETÜ iş birliğinde yürütülen ve çıktısı FPGA tabanlı ve OpenCL destekli, ölçeklenebilir ve özelleştirilebilir tasarıma sahip bir yardımcı işlemci ünitesi olan projenin donanım tasarımı kısmını kapsar. Bu çalışmada sinyal işleme uygulamalarında yaygın olarak kullanılan fonksiyonlar için özelleştirilmiş, OpenCL destekli ve ölçeklenebilir bir paralel işlemci mimarisi tasarlanmış ve FPGA platformunda gerçeklenmiştir.Typical digital signal processing algorithms executes the same DSP functions on different data sets. Parallelizing this process dramatically decreases execution time of such kind of functions. There are 4 popular platforms for parallelized applications: Many-core processors, GPGPUs, ASIC chips and FPGA based applications. Although each kind of platform has own pros and cons, GPGPU and FPGA based applications are more popular than others because of lower price and higher parallel processing capabilities. This MSc thesis consists of hardware design of FPGA based OpenCL ready highly scalable and configurable co-processor which is a project of ASELSAN and TOBB ETÜ. In this work, a scalable and configurable parallel processor architecture which supports OpenCL is designed and implemented on FPGA platform
Artifact of "CoMeT: Count-Min Sketch-based Aggressor Row Tracking to Mitigate RowHammer at Low Cost"
<p>Artifact evaluation of "CoMeT: Count-Min Sketch-based Aggressor Row Tracking to Mitigate RowHammer at Low Cost"</p>