Imc: Energy-Eicient In-Memory Convolver For Accelerating Binarized Deep Neural Network

Deep Convolutional Neural Networks (CNNs) are widely employed in modern AI systems due to their unprecedented accuracy in object recognition and detection. However, it has been proven that the main bottleneck to improve large scale deep CNN based hardware implementation performance is massive data communication between processing units and o-chip memory. In this paper, we pave a way towards novel concept of in-memory convolver (IMC) that could implement the dominant convolution computation within main memory based on our proposed Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array architecture to greatly reduce data communication and thus accelerate Binary CNN (BCNN). The proposed architecture could simultaneously work as non-volatile memory and a recongurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in conventional logic-in-memory designs. The computed logic output could be also simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. We employ such intrinsic in-memory processing architecture to eciently process data within memory to greatly reduce power-hungry and long distance data communication concerning state-of-the-art BCNN hardware. The hardware mapping results show that IMC can process the Binarized AlexNet on ImageNet data-set favorably with 134.27 J/img where ∼ 16× and 9× lower energy and area are achieved, respectively, compared to RRAM-based BCNN. Furthermore, 21.5% reduction in data movement in term of main memory accesses is observed compared to CPU/DRAM baseline

Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network

Over past years, the high demand to efficiently process deep learning (DL) models has driven the market of the chip design companies. However, the new Deep Chip architectures, a common term to refer to DL hardware accelerator, have slightly paid attention to the security requirements in quantized neural networks (QNNs), while the black/white -box adversarial attacks can jeopardize the integrity of the inference accelerator. Therefore in this paper, a comprehensive study of the resiliency of QNN topologies to black-box attacks is examined. Herein, different attack scenarios are performed on an FPGA-processor co-design, and the collected results are extensively analyzed to give an estimation of the impact\u27s degree of different types of attacks on the QNN topology. To be specific, we evaluated the sensitivity of the QNN accelerator to a range number of bitflip attacks (BFAs) that might occur in the operational lifetime of the device. The BFAs are injected at uniformly distributed times either across the entire QNN or per individual layer during the image classification. The acquired results are utilized to build the entropy-based model that can be leveraged to construct resilient QNN architectures to bit-flip attacks

Implementation of a National Wastewater Surveillance System in France as a Tool to Support Public Authorities During the Covid Crisis: The Obepine Project

International audienceThe Obépine project (OBservatoire EPIdémiologique daNs les Eaux usées) has brought together research teams with a variety of skills (virology, mathematics, hydrology, infectiology) to evaluate the relevance of a quantification for SARS-CoV-2 genomes and its variants in wastewater, to provide a new element for monitoring the COVID-19 epidemic. We have demonstrated the relevance of this strategy, which aims at quantifying the viral genome at the entrance of wastewater treatment plants thanks to the use of sensitive, quantifiable, and reproducible molecular techniques associated with an original mathematical model. Obépine monitored up to 200 wastewater treatment plants, on a bi-weekly basis, in metropolitan and overseas France which corresponds to more than 33% of the French population. This article summarizes the key steps in the construction of the Obépine project